公开(公告)号：US09728293B2

公开(公告)日：2017-08-08

申请号：US14455858

申请日：2014-08-08

Applicant: Sang-Young Kim ,  Kyung-Soo Rho ,  Ho-Jeong Moon ,  Hyuck Shin ,  Sun-Nyeong Jung

Inventor： Sang-Young Kim ,  Kyung-Soo Rho ,  Ho-Jeong Moon ,  Hyuck Shin ,  Sun-Nyeong Jung

IPC: G01N23/02 ,  G21K1/10 ,  G01N23/04 ,  H01L21/66

CPC classification number: H01L22/12 ,  G01N23/04 ,  G21K1/10 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48153

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

公开(公告)号：US20100177165A1

公开(公告)日：2010-07-15

申请号：US12686496

申请日：2010-01-13

Applicant: Hye-Kyong Oh ,  Ho-Jeong Moon

Inventor： Hye-Kyong Oh ,  Ho-Jeong Moon

IPC: H04N13/02 ,  G01N25/00

CPC classification number: G01N25/72

Abstract: A precondition reliability test of a semiconductor package, to determine a propensity of the package to delaminate, includes a baking test of drying the package, a moisture soaking test of moisturizing the dried package, a reflow test of heat-treating the moisturized package using hot air convection, and a three-dimensional imaging of the package to acquire a 3-D image of a surface of the package. The three-dimensional imaging is preferably carried out using a Moire interferometry technique during the course of the reflow test. Therefore, the delamination of the package can be observed in real time so that data on the start and rapid development of the delamination can be produced. The method also allows data which can be ordered as a Weibull Plot to be produced, thereby enabling a quantitative analysis of the reliability test results.

Abstract translation: 确定包装分层倾向的半导体封装的前提条件可靠性试验包括干燥包装的烘烤试验，对干燥包装进行保湿的湿气浸泡试验，使用热热处理保湿包装的回流试验 空气对流和包装的三维成像以获得包装表面的3-D图像。 在回流试验过程中，优选使用莫尔干涉测量法进行三维成像。 因此，可以实时观察包装的分层，从而可以产生分层开始和快速发展的数据。 该方法还允许生成可作为Weibull Plot排序的数据，从而实现可靠性测试结果的定量分析。

公开(公告)号：US06756668B2

公开(公告)日：2004-06-29

申请号：US10232344

申请日：2002-08-30

Applicant: Joong-Hyun Baek ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Yun-Hyeok Im

Inventor： Joong-Hyun Baek ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Yun-Hyeok Im

IPC: H01L2312

CPC classification number: H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

公开(公告)号：US07692291B2

公开(公告)日：2010-04-06

申请号：US10121515

申请日：2002-04-12

Applicant: Ho-Jeong Moon ,  Kyu-Jin Lee

Inventor： Ho-Jeong Moon ,  Kyu-Jin Lee

IPC: H01L23/02 ,  H01L23/12 ,  H01L23/10 ,  H01L23/28

CPC classification number: H01L25/0652 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2224/0401

Abstract: A circuit board having heating elements and a hermetically sealed multi-chip package. The multi-chip package includes a plurality of semiconductor chips, a substrate electrically coupled to the plurality of semiconductor chips, heat dissipation means, and a plurality of thermal interfaces disposed between the semiconductor chips and the heat dissipation means. The heat dissipation means forms a hermetically sealed cavity that encloses the semiconductor chips and at least a portion of the substrate. The circuit board includes a chip mounting surface, a chip mounting area on the chip mounting surface, the chip mounting area including a plurality of lands, and heating elements connected to the lands, the heating elements capable heating a joint formed between the lands and electrode pads of a semiconductor chip.

Abstract translation: 具有加热元件和气密多芯片封装的电路板。 多芯片封装包括多个半导体芯片，与多个半导体芯片电耦合的基板，散热装置以及设置在半导体芯片和散热装置之间的多个热界面。 散热装置形成封闭半导体芯片和基板的至少一部分的气密密封腔。 电路板包括芯片安装表面，芯片安装表面上的芯片安装区域，芯片安装区域包括多个焊盘，以及连接到焊盘的加热元件，加热元件能够加热形成在焊盘和电极之间的接合部 半导体芯片的焊盘。

公开(公告)号：US20150103974A1

公开(公告)日：2015-04-16

申请号：US14455858

申请日：2014-08-08

Applicant: SANG-YOUNG KIM ,  KYUNG-SOO RHO ,  HO-JEONG MOON ,  HYUCK SHIN ,  SUN-NYEONG JUNG

Inventor： SANG-YOUNG KIM ,  KYUNG-SOO RHO ,  HO-JEONG MOON ,  HYUCK SHIN ,  SUN-NYEONG JUNG

IPC: G21K1/10 ,  G01N23/04

CPC classification number: H01L22/12 ,  G01N23/04 ,  G21K1/10 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48153

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract translation: 设置X射线源，并且将检测器设置为与X射线源相邻。 试样夹持器设置在X射线源和检测器之间。 过滤器设置在X射线源和测试样本架之间。 滤光器具有板状半导体，粒状半导体或其组合。

公开(公告)号：US08448506B2

公开(公告)日：2013-05-28

申请号：US12704960

申请日：2010-02-12

Applicant: Yeo-Hoon Yoon ,  Ho-Jeong Moon

Inventor： Yeo-Hoon Yoon ,  Ho-Jeong Moon

IPC: G01N19/04

CPC classification number: G01N19/04 ,  G01N2033/0095

Abstract: Provided is a method for testing adhesion. The method includes forming thin films on a substrate; attaching an elastic plate to the substrate, wherein the elastic plate has a larger elastic coefficient than the substrate; and performing an adhesion test on the thin films using an adhesion test apparatus.

Abstract translation: 提供了一种测试附着力的方法。 该方法包括在衬底上形成薄膜; 将弹性板附接到所述基板，其中所述弹性板具有比所述基板更大的弹性系数; 并使用粘合试验装置对薄膜进行粘合试验。

公开(公告)号：US20100206062A1

公开(公告)日：2010-08-19

申请号：US12704960

申请日：2010-02-12

Applicant: Yeo-Hoon YOON ,  Ho-Jeong MOON

Inventor： Yeo-Hoon YOON ,  Ho-Jeong MOON

IPC: G01N19/04

CPC classification number: G01N19/04 ,  G01N2033/0095

Abstract: Provided is a method for testing adhesion. The method includes forming thin films on a substrate; attaching an elastic plate to the substrate, wherein the elastic plate has a larger elastic coefficient than the substrate; and performing an adhesion test on the thin films using an adhesion test apparatus.

Abstract translation: 提供了一种测试附着力的方法。 该方法包括在衬底上形成薄膜; 将弹性板附接到所述基板，其中所述弹性板具有比所述基板更大的弹性系数; 并使用粘合试验装置对薄膜进行粘合试验。

公开(公告)号：US20090146300A1

公开(公告)日：2009-06-11

申请号：US12292569

申请日：2008-11-21

Applicant: Se-Young Yang ,  Ho-Jeong Moon ,  Seung-Woo Kim ,  Hyun Kyung Han

Inventor： Se-Young Yang ,  Ho-Jeong Moon ,  Seung-Woo Kim ,  Hyun Kyung Han

IPC: H01L23/498

CPC classification number: H01L23/4985 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Example embodiments of a semiconductor package are provided. In accordance with an example embodiment, a semiconductor package may include an external terminal connected to a concave surface of a bottom pad, wherein the bottom pad is recessed into a substrate. In accordance with another example embodiment, a semiconductor package may include at least one external terminal, a flexible substrate having a first surface with a plurality of convex portions and a second surface opposite the first surface having a plurality of concave portions, wherein the at least one terminal is recessed into the substrate and at least one of the concave portions surrounds a portion of the at least one external terminal.

Abstract translation: 提供半导体封装的示例性实施例。 根据示例性实施例，半导体封装可以包括连接到底部焊盘的凹面的外部端子，其中底部焊盘凹入基板。 根据另一示例性实施例，半导体封装可以包括至少一个外部端子，具有多个凸部的第一表面的柔性基板和具有多个凹部的与第一表面相对的第二表面，其中至少 一个端子凹陷到基板中，并且至少一个凹部围绕至少一个外部端子的一部分。

公开(公告)号：US20060035453A1

公开(公告)日：2006-02-16

申请号：US11196243

申请日：2005-08-04

Applicant: Seung-Woo Kim ,  Pyeong-Wan Kim ,  Sang-Ho Ahn ,  Bo-Seong Kim ,  Ho-Jeong Moon ,  Tae-Seong Park ,  Hee-Guk Choi

Inventor： Seung-Woo Kim ,  Pyeong-Wan Kim ,  Sang-Ho Ahn ,  Bo-Seong Kim ,  Ho-Jeong Moon ,  Tae-Seong Park ,  Hee-Guk Choi

IPC: H01L21/44 ,  H01L23/52

CPC classification number: H05K1/111 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01327 ,  H05K3/06 ,  H05K3/282 ,  H05K3/3452 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0353 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: In the method, a conductive pad of the board is etched to a depth that is greater than 50% and less than 100% of a thickness of the conductive pad. Subsequently, a solder ball may be formed on the etched conductive pad. For example, the conductive pad may be copper.

Abstract translation: 在该方法中，将电路板的导电焊盘蚀刻到大于导电焊盘厚度的50％且小于100％的深度。 随后，可以在蚀刻的导电焊盘上形成焊球。 例如，导电焊盘可以是铜。

公开(公告)号：US06638638B2

公开(公告)日：2003-10-28

申请号：US09954026

申请日：2001-09-18

Applicant: Sang-Young Kim ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Seung-Kon Mok

Inventor： Sang-Young Kim ,  Ho-Jeong Moon ,  Dong-Kil Shin ,  Seung-Kon Mok

IPC: B22F300

CPC classification number: H01L24/10 ,  B23K1/0008 ,  B23K35/0222 ,  B23K35/0244 ,  B23K2101/40 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10257 ,  H05K2203/0465 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T428/12014 ,  Y10T428/12222 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A solder structure comprising a radially-curved exterior surface enclosing a predetermined-sized cavity used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar properties. By assembling the two planar elements in a tiered arrangement, one planar element having an annular conductive pad and the other planar element having either a corresponding annular or circular conductive pad, separated by a spherical solder compound comprised of solder and a fluxing agent, a hollow solder structure can be created during a melting and subsequent cooling of the solder compound. The plasticity/resiliency characteristics of the resulting hollow solder structure absorbs lateral movement of the two planar elements relative to each other without degradation of the solder joint.

Abstract translation: 焊料结构包括径向弯曲的外表面，其包围预定尺寸的空腔，用于在预定的导电接触点处柔性地接合两个具有不同性质的平面元件。 通过以分层布置组装两个平面元件，一个平面元件具有环形导电焊盘，另一个平面元件具有相应的环形或圆形导电焊盘，由由焊料和助熔剂构成的球形焊料化合物分开， 可以在焊料化合物的熔化和随后的冷却期间产生焊料结构。 所得中空焊料结构的可塑性/弹性特性吸收两个平面元件相对于彼此的横向移动，而不会降低焊接接头。