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    METHOD AND APPARATUS FOR STORE DEPENDENCE PREDICTION
    1.
    发明申请
    METHOD AND APPARATUS FOR STORE DEPENDENCE PREDICTION 有权
    存储依赖性预测的方法和装置

    公开(公告)号：US20150006452A1

    公开(公告)日：2015-01-01

    申请号：US13931872

    申请日：2013-06-29

    申请人： Ho-Seop KIM ,  Robert S. CHAPPELL ,  Choon Yip SOO

    发明人： Ho-Seop KIM ,  Robert S. CHAPPELL ,  Choon Yip SOO

    IPC分类号： G06N5/04

    CPC分类号： G06N5/04 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3855

    摘要： An apparatus and method for store dependence prediction is described. For example, one embodiment of the invention includes a processor comprising a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation and responsively setting an indication within an entry associated with each store operation in the store buffer; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.

    摘要翻译： 描述了用于存储相关性预测的装置和方法。 例如，本发明的一个实施例包括处理器，其包括用于在完成之前缓存存储操作的存储缓冲器，用于将数据存储到存储器层次的存储操作; 以及存储相关预测器，用于预测是否允许加载操作被推测地跳过每个存储操作，并且响应地在与存储缓冲器中的每个存储操作相关联的条目内设置指示; 其中加载操作检查存储缓冲器中的指示以确定是否在每个存储操作之前推测地执行。

    SOFTWARE FLOW TRACKING USING MULTIPLE THREADS
    3.
    发明申请
    SOFTWARE FLOW TRACKING USING MULTIPLE THREADS 有权
    使用多个线程的软件流程跟踪

    公开(公告)号：US20090172644A1

    公开(公告)日：2009-07-02

    申请号：US11965271

    申请日：2007-12-27

    申请人： Vijayanand Nagarajan ,  Ho-Seop Kim ,  Youfeng Wu ,  Rajiv Gupta

    发明人： Vijayanand Nagarajan ,  Ho-Seop Kim ,  Youfeng Wu ,  Rajiv Gupta

    IPC分类号： G06F9/44

    CPC分类号： G06F21/566 ,  G06F8/33 ,  G06F11/3636

    摘要： Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.

    摘要翻译： 公开了用于执行动态信息流跟踪的方法，系统和机器可读介质。 一种方法包括执行具有主线程的程序的操作，并且使用跟踪线程跟踪主线程对程序的操作的执行。 该方法还包括利用跟踪线程来更新与主线程的值相关联的污点值，以反映该值是否被污染，并且基于该着色值确定跟踪线程是否使用该值 主线程违反了特定的安全策略。

    Performing dynamic information flow tracking
    4.
    发明申请
    Performing dynamic information flow tracking 审中-公开
    执行动态信息流跟踪

    公开(公告)号：US20070240141A1

    公开(公告)日：2007-10-11

    申请号：US11394287

    申请日：2006-03-30

    申请人： Feng Qin ,  Cheng Wang ,  Ho-Seop Kim ,  Yuanyuan Zhou ,  Youfeng Wu

    发明人： Feng Qin ,  Cheng Wang ,  Ho-Seop Kim ,  Yuanyuan Zhou ,  Youfeng Wu

    IPC分类号： G06F9/45 ,  G06F9/44

    CPC分类号： G06F21/16 ,  G06F8/52 ,  G06F2221/2101

    摘要： In one embodiment, the present invention includes a method for instrumenting a code block with code to perform dynamic information flow tracking. Then during execution, it may be determined whether a pattern of input data to the code block has been previously received by the code block. If so, the code block may be executed, otherwise the instrumented code block may be executed. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种用于用代码执行动态信息流跟踪的代码块的检测方法。 然后在执行期间，可以确定代码块先前是否接收到代码块的输入数据的模式。 如果是这样，则可以执行代码块，否则可以执行检测的代码块。 描述和要求保护其他实施例。

    Balanced P-LRU tree for a “multiple of 3” number of ways cache
    10.
    发明授权
    Balanced P-LRU tree for a “multiple of 3” number of ways cache 有权
    平衡的P-LRU树为“多个3”的缓存方式

    公开(公告)号：US09348766B2

    公开(公告)日：2016-05-24

    申请号：US13994690

    申请日：2011-12-21

    申请人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    发明人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    IPC分类号： G06F13/00 ,  G06F12/12 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

    摘要翻译： 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。