公开(公告)号：US08760918B2

公开(公告)日：2014-06-24

申请号：US13137423

申请日：2011-08-15

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20140149607A1

公开(公告)日：2014-05-29

申请号：US14038892

申请日：2013-09-27

申请人： Hojun SHIM ,  Eunchan KIM

发明人： Hojun SHIM ,  Eunchan KIM

IPC分类号： G06F3/06 ,  G06F13/24 ,  G06F13/28

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0689 ,  G06F13/24 ,  G06F13/28

摘要： A data transfer method of a storage device which includes a host bus adaptor to communicate with an external host via a first interface and to communicate internally via a second interface is provided. The data transfer method may include issuing a write command and a read command to the host bus adaptor; performing a read direct memory access operation using the first interface in response to the write command and simultaneously performing a write direct memory access operation using the second interface in response to the read command; and generating frame information structure (FIS) sequences according to the second interface in response to the issued write command and the issued read command. The first interface may perform a full duplex data transfer and the second interface may perform a half-duplex data transfer.

摘要翻译： 提供一种存储装置的数据传输方法，其包括通过第一接口与外部主机进行通信并经由第二接口在内部进行通信的主机总线适配器。 数据传输方法可以包括向主机总线适配器发出写入命令和读取命令; 响应于写入命令，使用第一接口执行读取直接存储器访问操作，并响应于读取命令同时执行使用第二接口的写入直接存储器访问操作; 以及响应于发出的写入命令和发出的读取命令，根据第二接口生成帧信息结构（FIS）序列。 第一接口可以执行全双工数据传输，并且第二接口可以执行半双工数据传输。

公开(公告)号：US08027194B2

公开(公告)日：2011-09-27

申请号：US12457485

申请日：2009-06-12

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： One embodiment of a nonvolatile memory device includes a memory cell array including a plurality of multi-level cells, and a control unit configured to determine a characteristic of data to be stored in the memory cell array. The control unit is configured to select one of plural multi-bit programming methods based on the determination. Data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit data when there is a program fail of most significant bit data.

摘要翻译： 非易失性存储器件的一个实施例包括包括多个多电平单元的存储单元阵列，以及配置为确定要存储在存储单元阵列中的数据的特性的控制单元。 控制单元被配置为基于该确定来选择多个多位编程方法之一。 数据根据所选择的多位编程方法存储在存储单元阵列中，并且当存在最高有效位数据的程序失败时，多个多位编程方法中的至少一个保持最低有效位数据。

公开(公告)号：US20110035536A1

公开(公告)日：2011-02-10

申请号：US12732316

申请日：2010-03-26

申请人： Hojun Shim ,  Je-Hyuck Song

发明人： Hojun Shim ,  Je-Hyuck Song

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7211 ,  G11C16/3495

摘要： A non-volatile memory device which includes a non-volatile memory core including a memory cell array and a controller configured to generate wear-leveling information from internal operation information of the memory cell array after a write operation, independent of a request from an external device. The wear-leveling information is selectively provided to the external device.

摘要翻译： 一种非易失性存储器件，其包括包括存储器单元阵列的非易失性存储器核心和被配置为在写入操作之后从存储单元阵列的内部操作信息生成磨损均衡信息的控制器，独立于来自外部的请求 设备。 磨损均衡信息选择性地提供给外部设备。

公开(公告)号：US20090310408A1

公开(公告)日：2009-12-17

申请号：US12457485

申请日：2009-06-12

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

摘要翻译： 存储器系统设置有处理器，主存储器和闪存。 通过实现加速和高数据可靠性，可以提高存储系统的性能。 存储器系统包括非易失性存储器件和被配置为驱动控制程序以控制非易失性存储器件的控制器。 即使在完成对非易失性存储器件的第一访问操作之前，控制程序也执行用于非易失性存储器件的第二访问操作。

公开(公告)号：US09252603B2

公开(公告)日：2016-02-02

申请号：US13217962

申请日：2011-08-25

申请人： Hojun Shim

发明人： Hojun Shim

IPC分类号： H02J7/00 ,  H02H3/10 ,  H02J7/34

CPC分类号： H02J7/0016 ,  H02H3/10 ,  H02J7/345

摘要： An auxiliary power device includes an auxiliary power source having first and second charging cells connected in series, a cell balance circuit configured to sense a charging voltage between the first and second charging cells, generate a balance voltage based on the sensed charging voltage, and applies the generated balance voltage between the first and second charging cells, and a microprocessor configured to diagnose the first and second charging cells based on the sensed charging cells and control the cell balance circuit.

摘要翻译： 辅助电源装置包括具有串联连接的第一和第二充电单元的辅助电源，电池平衡电路，被配置为感测第一和第二充电单元之间的充电电压，基于感测的充电电压产生平衡电压，并应用 第一和第二充电单元之间产生的平衡电压以及被配置为基于所感测的充电单元诊断第一和第二充电单元并控制单元平衡电路的微处理器。

公开(公告)号：US08990462B2

公开(公告)日：2015-03-24

申请号：US14038892

申请日：2013-09-27

申请人： Hojun Shim ,  Eunchan Kim

发明人： Hojun Shim ,  Eunchan Kim

IPC分类号： G06F3/06 ,  G06F13/24 ,  G06F13/28 ,  G06F13/38

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0689 ,  G06F13/24 ,  G06F13/28

摘要： A data transfer method of a storage device which includes a host bus adaptor to communicate with an external host via a first interface and to communicate internally via a second interface is provided. The data transfer method may include issuing a write command and a read command to the host bus adaptor; performing a read direct memory access operation using the first interface in response to the write command and simultaneously performing a write direct memory access operation using the second interface in response to the read command; and generating frame information structure (FIS) sequences according to the second interface in response to the issued write command and the issued read command. The first interface may perform a full duplex data transfer and the second interface may perform a half-duplex data transfer.

摘要翻译： 提供一种存储装置的数据传输方法，其包括通过第一接口与外部主机进行通信并经由第二接口在内部进行通信的主机总线适配器。 数据传输方法可以包括向主机总线适配器发出写入命令和读取命令; 响应于写入命令，使用第一接口执行读取直接存储器访问操作，并响应于读取命令同时执行使用第二接口的写入直接存储器访问操作; 以及响应于发出的写入命令和发出的读取命令，根据第二接口生成帧信息结构（FIS）序列。 第一接口可以执行全双工数据传输，并且第二接口可以执行半双工数据传输。

公开(公告)号：US08856503B2

公开(公告)日：2014-10-07

申请号：US12656715

申请日：2010-02-16

申请人： Hojun Shim

发明人： Hojun Shim

IPC分类号： G06F15/177 ,  G06F9/44

CPC分类号： G06F9/4401

摘要： The booting method of a computing system includes determining whether boot data of an operating system is pinned to a main memory, reading boot data from a storage device to pin the read boot data to the main memory when relocation of the pinned boot data is required, and performing a booting operation using the pinned boot data.

摘要翻译： 计算系统的启动方法包括：确定操作系统的启动数据是否被固定到主存储器，当需要重新定位被固定的引导数据时，从存储设备读取引导数据以将读引导数据引导到主存储器， 并使用固定引导数据执行引导操作。

公开(公告)号：US08705272B2

公开(公告)日：2014-04-22

申请号：US13137424

申请日：2011-08-15

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

摘要翻译： 存储器系统设置有处理器，主存储器和闪存。 通过实现加速和高数据可靠性，可以提高存储系统的性能。 存储器系统包括非易失性存储器件和被配置为驱动控制程序以控制非易失性存储器件的控制器。 即使在完成对非易失性存储器件的第一访问操作之前，控制程序也执行用于非易失性存储器件的第二访问操作。

公开(公告)号：US08625344B2

公开(公告)日：2014-01-07

申请号：US13137425

申请日：2011-08-15

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.