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    Memory system with a layer comprising a dedicated redundancy area
    2.
    发明授权
    Memory system with a layer comprising a dedicated redundancy area 有权
    具有包括专用冗余区域的层的存储器系统

    公开(公告)号：US08891322B2

    公开(公告)日：2014-11-18

    申请号：US13621486

    申请日：2012-09-17

    Applicant: Hong Beom Pyeon

    Inventor： Hong Beom Pyeon

    IPC: G11C29/00 ,  G11C29/44 ,  G11C29/12

    CPC classification number: G11C29/785 ,  G11C29/44 ,  G11C2029/1206 ,  G11C2029/4402

    Abstract: Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.

    Abstract translation: 公开了可以包括包括第一冗余存储器元件，输入/输出接口，第一层保险丝盒和保险丝熔断控制的第一层的系统和方法。 这些系统和方法还可以包括通过包括耦合到第一冗余存储器元件的第二层存储器元件和第二层熔丝盒的第一连接耦合到第一层的第二层。 此外，这些系统和方法还可以包括耦合到第一层的冗余寄存器，其中当第二层存储器元件的一部分出现故障时，冗余寄存器向熔丝熔断控制提供信息，其分配第一冗余存储器的一部分 元件，以通过在第一层熔丝盒和第二层熔丝盒中吹入元件来为第二层存储元件的故障部分提供冗余。

    Clock reproducing and timing method in a system having a plurality of devices
    3.
    发明授权
    Clock reproducing and timing method in a system having a plurality of devices 有权
    具有多个装置的系统中的时钟再现和定时方法

    公开(公告)号：US08781053B2

    公开(公告)日：2014-07-15

    申请号：US12168091

    申请日：2008-07-04

    Applicant: Hong Beom Pyeon ,  Peter Gillingham

    Inventor： Hong Beom Pyeon ,  Peter Gillingham

    IPC: H03D3/24

    CPC classification number: H04L7/0331 ,  G06F13/1689 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  Y02D10/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.

    Abstract translation: 系统包括存储器控制器和串联连接的多个半导体器件。 每个设备具有用于存储数据的存储器核心。 存储器控制器提供用于同步器件的操作的时钟信号。 每个器件包括被PLL使能信号选择性地使能或禁止的锁相环（PLL）。 在每个组中，选定数量的器件的PLL通过PLL使能信号使能，其他器件被禁止。 所启用的PLL响应于输入时钟信号提供多个具有90°的倍数的相移的再现时钟信号。 数据传输与再现的时钟信号中的至少一个同步。 在禁用PLL的器件中，数据传输与输入时钟信号同步。 使能的PLL和禁用的PLL分别使器件成为源和公共同步时钟。 设备可以分组。 一组的器件可以由多个芯片封装构成。

    Packet based ID generation for serially interconnected devices
    4.
    发明授权
    Packet based ID generation for serially interconnected devices 有权
    用于串行互连设备的基于分组的ID生成

    公开(公告)号：US08700818B2

    公开(公告)日：2014-04-15

    申请号：US11529293

    申请日：2006-09-29

    Applicant: Hong Beom Pyeon ,  HakJune Oh

    Inventor： Hong Beom Pyeon ,  HakJune Oh

    IPC: G06F3/00 ,  G06F1/12

    CPC classification number: G06F1/12 ,  G06F1/04 ,  G11C5/00 ,  G11C5/066 ,  G11C7/20

    Abstract: Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

    Abstract translation: 各种存储器件（例如，DRAM，闪存）串联连接。 存储器件需要它们的标识符（ID）。 每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。 命令数据和先前生成的ID数据被同步地注册。 注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。 计算是一个加法或减法。 通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。 响应于解释的ID和时钟来控制时钟延迟。 根据受控时钟延迟，以分组为基础提供新的ID。 在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

    Hierarchical common source line structure in NAND flash memory
    5.
    发明授权
    Hierarchical common source line structure in NAND flash memory 有权
    NAND闪存中的分层公共源线结构

    公开(公告)号：US08675410B2

    公开(公告)日：2014-03-18

    申请号：US13481888

    申请日：2012-05-28

    Applicant: Hong-Beom Pyeon ,  Jin-Ki Kim

    Inventor： Hong-Beom Pyeon ,  Jin-Ki Kim

    IPC: G11C11/34

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

    Abstract: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.

    Abstract translation: 通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。 集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。 对于源行页面编程，分发线可以称为全局公用源线（GCSL）。 在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。 为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。 此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

    Phase change memory word line driver
    7.
    发明授权
    Phase change memory word line driver 有权
    相变存储器字线驱动器

    公开(公告)号：US08526227B2

    公开(公告)日：2013-09-03

    申请号：US13110399

    申请日：2011-05-18

    Applicant: Hong Beom Pyeon

    Inventor： Hong Beom Pyeon

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0071

    Abstract: A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.

    Abstract translation: 一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。 可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。 通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。

    MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION
    10.
    发明申请
    MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION 有权
    具有双重功能的多级电池访问缓冲器

    公开(公告)号：US20120320674A1

    公开(公告)日：2012-12-20

    申请号：US13595466

    申请日：2012-08-27

    Applicant: Hong Beom PYEON

    Inventor： Hong Beom PYEON

    IPC: G11C16/04

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5642 ,  G11C2211/5647

    Abstract: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.

    Abstract translation: 提供了使用两级MLC（多级单元）操作的诸如页面缓冲器的访问缓冲器，用于写入诸如Flash的非易失性存储器。 访问缓冲器具有用于临时存储要写入的数据的第一锁存器。 提供第二锁存器用于从作为两级写入操作的一部分的数据从存储器读取数据。 第二个锁存器具有从存储器读取时参与锁存功能的反相器。 相同的反相器用于产生正被写入第一锁存器的输入信号的补码，结果是使用双端输入来写入第一锁存器。

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