公开(公告)号：US08228069B2

公开(公告)日：2012-07-24

申请号：US12344024

申请日：2008-12-24

申请人： Sun-Jung Lee ,  Hong-Jae Shin

发明人： Sun-Jung Lee ,  Hong-Jae Shin

IPC分类号： G01R31/08

CPC分类号： G01R31/31717 ,  G11C11/41 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008

摘要： A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.

摘要翻译： 测试装置包括在半导体衬底上的多对测试触点; 第一测试结构，其包括多个第一测试互连层和电连接到第一测试互连层的第一体互连层，每个第一测试互连层电连接到至少一个测试接触; 以及第二测试结构，其包括多个第二测试互连层和电连接到第二测试互连层的第二体互连层，每个第二测试互连层电连接到至少一个测试接触。

公开(公告)号：US07785951B2

公开(公告)日：2010-08-31

申请号：US11831223

申请日：2007-07-31

申请人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US07759185B2

公开(公告)日：2010-07-20

申请号：US11853187

申请日：2007-09-11

申请人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.

摘要翻译： 半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜 第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。 半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔 层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔 暴露第三栅电极的界面区域。 形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔 形成了。

公开(公告)号：US20100173497A1

公开(公告)日：2010-07-08

申请号：US12655837

申请日：2010-01-06

申请人： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Seo-Woo Nam ,  In-Keun Lee ,  Jung-Hoon Lee

发明人： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Seo-Woo Nam ,  In-Keun Lee ,  Jung-Hoon Lee

IPC分类号： H01L21/306

CPC分类号： H01L21/32139

摘要： A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern.

摘要翻译： 制造半导体集成电路器件的方法包括：提供衬底; 在基板上依次形成被蚀刻层，第一层和第二层; 在所述第一层和第二层上形成第一蚀刻掩模，所述第一蚀刻掩模具有以第一间距彼此分开并沿第一方向延伸的多个第一线图案; 使用第一蚀刻掩模在第二层和第一层上顺序地执行第一蚀刻以形成具有第二和第一图案的中间掩模图案; 在所述中间掩模图案上形成第二蚀刻掩模，所述第二蚀刻掩模包括以第二间距彼此分开并沿除了所述第一方向之外的第二方向延伸的多个第二线图案; 在第二图案的一部分上使用第二蚀刻掩模进行第二蚀刻，使得第二图案的剩余部分留在第一图案上; 在与第一图案上的第二蚀刻和中间掩模图案的第二图案的剩余部分不同的条件下，使用第二蚀刻掩模进行第三蚀刻，并形成最终的掩模图案; 并使用最终的掩模图案来图案化待蚀刻的层。

公开(公告)号：US07706159B2

公开(公告)日：2010-04-27

申请号：US11442451

申请日：2006-05-26

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

IPC分类号： G05F1/10

CPC分类号： H02M3/073

摘要： A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.

摘要翻译： 用于DC-DC转换器的电荷泵包括接收输入电压的输入端子，输出输出电压的输出端子，串联连接在输入端子和输出端子之间的多个电荷泵浦级，以及电压电平转换器 第一和第二栅极时钟信号的电压电平，使得接收的第一和第二栅极时钟信号具有预定的幅度。 因此，电荷泵可以通过使VGS的幅度最大化来提高功率效率。 使用电荷泵的DC-DC转换器也可以应用于便携式设备，以最小化功耗，并且提供了一种用于提高DC-DC转换器的功率效率的方法。

公开(公告)号：US07655525B2

公开(公告)日：2010-02-02

申请号：US11848991

申请日：2007-08-31

申请人： Sun-jung Lee ,  Hong-jae Shin ,  Bong-seok Suh

发明人： Sun-jung Lee ,  Hong-jae Shin ,  Bong-seok Suh

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/4763

CPC分类号： H01L29/66515 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.

摘要翻译： 根据本发明的示例性实施例的防止栅极间隔物应力和硅化物区域的物理和化学损伤的半导体器件及其制造方法包括：衬底，形成在衬底中的隔离区域，栅极图案 形成在衬底上的隔离区域之间，与栅极图案的侧壁相邻并延伸到衬底表面的L型衬垫，形成在衬底上的L型间隔物延伸的端部之间的源极/漏极硅化物区域 通过与源极/漏极硅化物区域电连接的插塞到衬底的表面和隔离区域，与L型间隔物相邻并填充形成在栅极上的通孔塞层之间的空间的层间电介质层 图案和衬底，以及形成在层间电介质层上的信号传输线。

公开(公告)号：US07635645B2

公开(公告)日：2009-12-22

申请号：US11028515

申请日：2005-01-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76829

摘要： Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

摘要翻译： 公开了形成互连线和互连线结构的方法。 该方法包括在半导体衬底上形成层间绝缘层，其中层间绝缘层由碳掺杂的低k电介质层形成。 在层间绝缘层上形成氧化阻隔层。 在氧化阻挡层上形成氧化物覆盖层。 通孔位于氧化物覆盖层，氧化阻挡层和层间绝缘层中。 导电层图案形成在通孔内。

公开(公告)号：US20090280637A1

公开(公告)日：2009-11-12

申请号：US12453326

申请日：2009-05-07

申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31695

摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层 半导体器件。 该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔， 形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

公开(公告)号：US20090167319A1

公开(公告)日：2009-07-02

申请号：US12344024

申请日：2008-12-24

申请人： Sun-Jung Lee ,  Hong-Jae Shin

发明人： Sun-Jung Lee ,  Hong-Jae Shin

IPC分类号： G01R31/28

CPC分类号： G01R31/31717 ,  G11C11/41 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008

摘要： A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.

摘要翻译： 测试装置包括在半导体衬底上的多对测试触点; 第一测试结构，其包括多个第一测试互连层和电连接到第一测试互连层的第一体互连层，每个第一测试互连层电连接到至少一个测试接触; 以及第二测试结构，其包括多个第二测试互连层和电连接到第二测试互连层的第二体互连层，每个第二测试互连层电连接到至少一个测试接触。

公开(公告)号：US20090085075A1

公开(公告)日：2009-04-02

申请号：US12196454

申请日：2008-08-22

申请人： Ki-chul KIM ,  Hong-Jae Shin ,  Jung-Deog Lee

发明人： Ki-chul KIM ,  Hong-Jae Shin ,  Jung-Deog Lee

IPC分类号： H01L29/78 ,  H01L21/3205 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/28044 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： A method of fabricating a MOS transistor, and a MOS transistor fabricated by the method. The method can include forming a gate pattern on a semiconductor substrate. The gate pattern can be formed by sequentially stacking a gate electrode and a capping layer pattern. The capping layer pattern is formed to have a lower capping layer pattern and an upper capping layer pattern. The lower capping layer pattern is formed to a smaller width than the upper capping layer pattern.

摘要翻译： 一种制造MOS晶体管的方法和通过该方法制造的MOS晶体管。 该方法可以包括在半导体衬底上形成栅极图案。 栅极图案可以通过顺序堆叠栅电极和覆盖层图案来形成。 盖层图案形成为具有较低的封盖层图案和上覆盖层图案。 下盖层图案形成为比上盖层图案小的宽度。