公开(公告)号：US08063654B2

公开(公告)日：2011-11-22

申请号：US12505215

申请日：2009-07-17

申请人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

发明人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

IPC分类号： G01R31/26

CPC分类号： G01R31/318544 ,  H01L2224/16145

摘要： An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.

摘要翻译： 集成电路器件包括堆叠管芯和具有探针焊盘的基座，该探针焊盘直接耦合到基座芯片的测试逻辑，以实现用于集成电路器件测试的扫描链。 基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。 基座芯片还包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探测焊盘。 基准芯片的测试逻辑被配置为耦合到堆叠芯片的附加测试逻辑以实现扫描链。 探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来实现扫描链。

公开(公告)号：US6010958A

公开(公告)日：2000-01-04

申请号：US907005

申请日：1997-08-06

申请人： Tung-Po Chen ,  Bing-Chang Wu ,  Hong-Tsz Pan

发明人： Tung-Po Chen ,  Bing-Chang Wu ,  Hong-Tsz Pan

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/3105 ,  H01L21/76819 ,  Y10S438/937

摘要： A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.

摘要翻译： 一种在制造金属互连件时改善电介质层的平面化的方法，其中使用快速热处理操作以便在介电层局部平坦化之后固化电介质层的暴露表面。 该方法避免了在预金属蚀刻操作期间对介电层的损坏，因此，防止在随后的钨沉积期间残留的钨变成楔形，从而产生可能导致与金属布线接触的短路的桁条。

公开(公告)号：US5902752A

公开(公告)日：1999-05-11

申请号：US648618

申请日：1996-05-16

申请人： Shin-Wei Sun ,  Water Lur ,  Ming-Tzong Yang ,  Hong-Tsz Pan

发明人： Shin-Wei Sun ,  Water Lur ,  Ming-Tzong Yang ,  Hong-Tsz Pan

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L23/528 ,  H01L27/02 ,  H01L21/283

CPC分类号： H01L27/0207 ,  H01L21/31053 ,  H01L21/76229 ,  H01L23/528 ,  H01L2924/0002

摘要： A method of designing an active layer mask with a dummy pattern by computer aided design (CAD) in shallow trench isolation using chemical mechanical polishing (CMP) to achieve global planarization. In this method, an original mask is provided with an active region including a diffusion area pattern, a polysilicon area pattern and a well area pattern. The diffusion area pattern and the polysilicon area pattern are expanded by an area of dimension a and the well area pattern is extended inward and outward to an area of dimension b. The expanded diffusion, polysilicon and well areas form a first pattern area. The first pattern area is subtracted from the whole region to obtain a second pattern area. A third pattern area is obtained by performing an AND operation on a dummy array pattern and the second pattern area. Expanding the third pattern area to an area of dimension c, a fourth pattern area is obtained. Finally an active layer mask with a dummy pattern is obtained by performing an OR operation on the fourth pattern area and the diffusion area pattern.

摘要翻译： 通过计算机辅助设计（CAD）在使用化学机械抛光（CMP）的浅沟槽隔离中设计具有虚拟图案的有源层掩模的方法来实现全局平面化。 在该方法中，原始掩模设置有包括扩散区域图案，多晶硅区域图案和阱区域图案的有源区域。 扩散区域图案和多晶硅区域图案通过尺寸a的面积扩大，并且阱区域图案向内和向外延伸到尺寸为b的区域。 扩展的扩散，多晶硅和阱区形成第一模式区域。 从整个区域中减去第一图案区域以获得第二图案区域。 通过对虚拟阵列图案和第二图案区域执行AND运算来获得第三图案区域。 将第三图案区域扩展到尺寸c的区域，获得第四图案区域。 最后，通过对第四图案区域和扩散区域图案执行OR运算来获得具有虚拟图案的有源层掩模。

公开(公告)号：US5449644A

公开(公告)日：1995-09-12

申请号：US181298

申请日：1994-01-13

申请人： Gary Hong ,  Cheng H. Huang ,  Ming-Tzong Yang ,  Hong-Tsz Pan

发明人： Gary Hong ,  Cheng H. Huang ,  Ming-Tzong Yang ,  Hong-Tsz Pan

IPC分类号： H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76802 ,  Y10S148/133

摘要： A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.

摘要翻译： 描述了通过使用牺牲旋涂玻璃层形成接触开口的新方法。 提供半导体衬底，其中衬底的表面具有不平坦的形貌。 在基体的不平坦表面上沉积有胶层，并在低温下回流，由此在层叠的接触开口区域上形成沟槽形表面。 玻璃层被旋涂玻璃层覆盖，其中旋涂玻璃将基材的表面平坦化。 将旋涂玻璃层烘烤，然后用均匀的厚度的光致抗蚀剂层覆盖。 光致抗蚀剂层被曝光和显影以形成用于接触开口的所需光刻胶掩模。 暴露的旋涂玻璃和玻璃层被蚀刻掉以提供到半导体衬底的接触开口。 剥离光致抗蚀剂层，去除牺牲旋涂玻璃层，以在集成电路的制造中完成接触开口的形成。

公开(公告)号：US08878337B1

公开(公告)日：2014-11-04

申请号：US13186279

申请日：2011-07-19

申请人： Hong-Tsz Pan ,  Yun Wu ,  Shuxian Wu ,  Qi Lin ,  Bang-Thu Nguyen

发明人： Hong-Tsz Pan ,  Yun Wu ,  Shuxian Wu ,  Qi Lin ,  Bang-Thu Nguyen

IPC分类号： H01L21/02

CPC分类号： H01L29/94 ,  H01L21/3212 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/66181 ,  H01L29/66545 ,  H01L29/78

摘要： A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.

摘要翻译： 一种用于减轻由化学机械抛光引起的金属栅极凹陷的方法和集成电路结构。 集成电路结构包括包括至少一个第一类型装置的第一区域; 第二区域，包括至少一个第二类型装置; 第三区域包括至少一个具有多晶硅最上层的电容器，其中电容器面积大于第一和第二区域的总和。 该方法利用电容器的多晶硅来减轻至少一个器件的金属栅极的金属栅极凹陷。

公开(公告)号：US08296689B1

公开(公告)日：2012-10-23

申请号：US12419234

申请日：2009-04-06

申请人： Arifur Rahman ,  Hong-tsz Pan

发明人： Arifur Rahman ,  Hong-tsz Pan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Method, apparatus, and computer readable medium for designing an integrated circuit (IC) are described. In some examples, layout data describing conductive layers of the integrated circuit is obtained. The layout data is analyzed to identify through die via (TDV) areas. A metal fill pattern is created for each of the TDV areas having a maximum metal density within design rules for the integrated circuit. The metal fill pattern for each of the TDV areas is merged with the layout data.

摘要翻译： 描述了用于设计集成电路（IC）的方法，装置和计算机可读介质。 在一些示例中，获得了描述集成电路的导电层的布局数据。 分析布局数据，以便通过（TDV）区域识别。 为集成电路的设计规则中具有最大金属密度的每个TDV区域创建金属填充图案。 每个TDV区域的金属填充图案与布局数据合并。

公开(公告)号：US08266553B1

公开(公告)日：2012-09-11

申请号：US12141543

申请日：2008-06-18

申请人： Bang-Thu Nguyen ,  Yan Wang ,  Hong-tsz Pan ,  Xin Wu

发明人： Bang-Thu Nguyen ,  Yan Wang ,  Hong-tsz Pan ,  Xin Wu

IPC分类号： G06F17/50

CPC分类号： G03F1/84

摘要： An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.

摘要翻译： 公开了一种用于检测掩模数据处理错误的集成电路器件布局和方法，其中集成电路器件布局包括其中设置可操作电路的器件区域。 集成电路装置布局还包括其中设置有验证元件的验证区域。 验证元件包括在设备区域中是至少一些不同类型的单元的重复的单元，并且可以包括在设备区域中至少一些类型的结构的重复的结构。 验证区域中的模式用于最终验证过程，以识别掩模工作台中的掩码数据处理错误。 由于验证区域中的模式易于定位和识别，所以执行最终验证过程所需的时间减少，并且最终验证过程中的错误机会减少。

公开(公告)号：US06670249B1

公开(公告)日：2003-12-30

申请号：US09686879

申请日：2000-10-12

申请人： Hong-Tsz Pan ,  Tung-Po Chen

发明人： Hong-Tsz Pan ,  Tung-Po Chen

IPC分类号： H01L21336

CPC分类号： H01L21/28518

摘要： A process for forming high temperature stable self-aligned suicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal suicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal suicide layer profile can be ensured even if subsequent high temperature processing operations are performed.

摘要翻译： 用于形成高温稳定的自对准硅化物层的方法，不仅在硅化反应中使用高温而不仅能够均匀且均匀地形成，而且还可以经受其它后续的高温热处理操作并保持稳定的金属硅化物层 之后的档案。 而且，通过适当地调节非晶注入参数，可以获得所需的金属硅化物层的厚度和均匀性，而使用氮化钛盖层有助于在高温形成期间稳定金属硅化物层，并且稳定且均匀的金属硅化物 即使执行后续的高温处理操作，也可以确保层的轮廓。

公开(公告)号：US6022795A

公开(公告)日：2000-02-08

申请号：US73861

申请日：1998-05-07

申请人： Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

发明人： Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

公开(公告)号：US5650346A

公开(公告)日：1997-07-22

申请号：US557546

申请日：1995-11-14

申请人： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

发明人： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by:forming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

摘要翻译： 一种MOSFET器件，其具有覆盖有介电材料的衬底，该器件包括电容耦合到多晶硅电极的多个掩埋导体，其通过以下方式制成：在包含MOSFET器件的区域之间形成通过离子注入穿过衬底中的多个位线的区域 栅极氧化物以预定图案进入衬底，并且在电介质材料上形成跨越位线的多晶硅电极。