公开(公告)号：US4454580A

公开(公告)日：1984-06-12

申请号：US302932

申请日：1981-09-16

申请人： Howard L. Page ,  James A. Wingert

发明人： Howard L. Page ,  James A. Wingert

IPC分类号： G06F9/40 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F9/50 ,  G06F12/02 ,  G06F9/00

CPC分类号： G06F9/5016 ,  G06F12/0284 ,  G06F9/30054 ,  G06F9/3851

摘要： A computer architecture is disclosed which permits intersegment program calls with associated selective allocation of data segments of varying lengths. The calling program controls selective allocation of segments to the called program but the called program controls the lengths of the segments being allocated. In this way, recursive calls to the same program cannot affect the function or data of other programs or of the same program in a previous call. Also allocation of data segments can be postponed until execution resulting in more flexible execution of programs written without knowledge of the details of other co-executing programs.

摘要翻译： 公开了一种计算机架构，其允许具有不同长度的数据段的相关选择性分配的段间节目调用。 调用程序控制对被调用程序的段的选择性分配，但被调用程序控制被分配段的长度。 以这种方式，对同一程序的递归调用不会影响其他程序的功能或数据，也不影响先前调用中相同的程序。 数据段的分配可以推迟到执行之前，导致在不了解其他协同执行程序的细节的情况下编写的程序的更灵活的执行。

公开(公告)号：US4155117A

公开(公告)日：1979-05-15

申请号：US819913

申请日：1977-07-28

申请人： Matthew J. Mitchell, Jr. ,  Howard L. Page

发明人： Matthew J. Mitchell, Jr. ,  Howard L. Page

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F15/17 ,  G06F3/04

CPC分类号： G06F15/17 ,  G06F13/122

摘要： A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.

摘要翻译： 用于互连两个或多个数字计算机或数字数据处理器的高性能通道到通道适配器。 多个输入/输出设备地址由通道到通道适配器识别。 通道到通道适配器通过匹配设备地址使适当的处理器到处理器连接。 特别地，为了数据传输目的，它互连用于已经接收到相同设备地址的两个处理器。 处理器使用的设备地址分配和数据传输的方向是通过在互连处理器上执行的软件系统中达成的约定。 通道到通道适配器没有这些约定的视图。 在更一般的情况下，通过软件惯例将两个设备地址分配给每个处理器到处理器链路，一个地址用于在一个方向上传送数据，另一个地址用于沿相反方向传输数据。

公开(公告)号：US4445176A

公开(公告)日：1984-04-24

申请号：US107806

申请日：1979-12-28

申请人： John L. Burk ,  Roger L. Cormier ,  Michael H. Hartung ,  Ray A. Larner ,  Donald J. Lucas ,  Kenneth R. Lynch ,  Brian B. Moore ,  Howard L. Page ,  David H. Wansor ,  Carl Zeitler, Jr.

发明人： John L. Burk ,  Roger L. Cormier ,  Michael H. Hartung ,  Ray A. Larner ,  Donald J. Lucas ,  Kenneth R. Lynch ,  Brian B. Moore ,  Howard L. Page ,  David H. Wansor ,  Carl Zeitler, Jr.

IPC分类号： G06F13/00 ,  G06F13/12 ,  G06F15/167

CPC分类号： G06F15/167 ,  G06F13/122

摘要： Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request. An "adapter" processor associated with each host and subsystem operates on an asynchronous basis to transfer messages and data relative to the associated host or subsystem. One or more processing "engines" in each adapter communicates with one or more CPU's in the associated host or subsystem through an associated "adapter store". A portion of each adapter store is used as a buffer pool for constructing "subchannel control spaces" to control transers of messages and data. Elements of each subchannel control space are returned to free status as soon as they are not needed for sustaining associated transfers.

摘要翻译： 辅助存储子系统与主机数据处理系统交换消息和数据，并在主机系统之间转发消息。 因此，主机系统除了能够访问子系统存储器中的数据之外还相互通信。 通过从主机发送到子系统的“请求”启动对子系统存储的访问。 每个请求是包含一个或多个命令的数组的消息，每个命令指定要由子系统执行的数据传送或控制功能。 子系统可以一次处理多个请求。 它还可以以适合于子系统资源的可用性和到主机系统的数据链路的任意顺序处理请求中的命令。 在处理请求中的所有命令之后，子系统向发起请求的主机系统发送关联的“完成”消息。 完成消息指示相关请求中的每个命令的完成状态或异常终止。 与每个主机和子系统相关联的“适配器”处理器在异步的基础上操作以相对于相关联的主机或子系统传送消息和数据。 每个适配器中的一个或多个处理“引擎”通过相关联的“适配器存储”与相关主机或子系统中的一个或多个CPU进行通信。 每个适配器存储的一部分用作缓冲池，用于构建“子信道控制空间”来控制消息和数据的传输。 每个子通道控制空间的元素一旦不需要维持相关的传输就返回到空闲状态。