公开(公告)号：US20160313746A1

公开(公告)日：2016-10-27

申请号：US15101912

申请日：2015-07-16

申请人： Chunyu WU ,  Hsin-Hui LEE

发明人： Hsin-Hui Lee

IPC分类号： G05D16/20

CPC分类号： G05D16/2066 ,  F17D1/02 ,  F17D1/04 ,  F17D1/20 ,  F17D3/01

摘要： System and method for gas pressure stabilization. The system comprises a pressure stabilizer which is divided into a receiving chamber and a pressure chamber by a flexible membrane, a booster device, a gas divider, and a control driver that can sense movement of the flexible membrane and control the gas divider accordingly. A pressure pilot is used to set the desired pressure in the pressure chamber. The pressure of the receiving chamber will stabilize to be the same with that of the pressure chamber regardless of the gas flow change or gas pressure change at the gas source, or the pressure fluctuation in the downstream system. The gas passing the system can eventually be recycled to a recycling system in the downstream without harming the environment.

摘要翻译： 气压稳定系统及方法。 该系统包括压力稳定器，其通过柔性膜分为接收室和压力室，增压装置，气体分配器和控制驱动器，其可以感测柔性膜的运动并相应地控制气体分配器。 使用压力导向器来设定压力室中的所需压力。 接收室的压力将稳定为与压力室的压力相同，而与气源的气体流量变化或气体压力变化或下游系统中的压力波动无关。 通过系统的气体最终可以循环利用到下游的回收系统，而不会影响环境。

公开(公告)号：US08497584B2

公开(公告)日：2013-07-30

申请号：US10810965

申请日：2004-03-26

申请人： Yen-Ming Chen ,  Chia-Fu Lin ,  Shun-Liang Hsu ,  Kai-Ming Ching ,  Hsin-Hui Lee ,  Chao-Yuan Su ,  Li-Chih Chen

发明人： Yen-Ming Chen ,  Chia-Fu Lin ,  Shun-Liang Hsu ,  Kai-Ming Ching ,  Hsin-Hui Lee ,  Chao-Yuan Su ,  Li-Chih Chen

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11912 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

摘要翻译： 提供了一种创建焊料凸块的新方法。 最初遵循常规方法，在接触垫的表面上形成凹凸金属图案层。 随后沉积一层光致抗蚀剂，该光致抗蚀剂层被图案化和显影，产生具有与接触焊盘对准的T形开口的抗蚀剂掩模。 该T形开口填充有焊料化合物，在UBM层的表面上形成T形焊料化合物层。 去除光致抗蚀剂层，暴露所生成的T形焊料化合物层，进一步暴露UBM层。 使用焊料化合物的T形层作为掩模蚀刻UBM层。 焊料复合物的回流导致产生焊球。

公开(公告)号：US07952167B2

公开(公告)日：2011-05-31

申请号：US11796202

申请日：2007-04-27

申请人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Shin-Puu Jeng ,  Shang-Yun Hou

发明人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Shin-Puu Jeng ,  Shang-Yun Hou

IPC分类号： H01L29/06

CPC分类号： H01L23/544 ,  H01L23/585 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing.

摘要翻译： 提出了一种划线设计，以减少锯切锯片造成的损坏。 一个实施例包括位于划线内且至少部分地位于划线内的金属板。 这些金属板中的每一个具有一个或多个槽以帮助减轻压力。 或者，代替金属板，可以将填充有金属的凹槽放置在划线中。 这些金属板也可以与密封环同时使用，以便在锯切期间更好地保护。

公开(公告)号：US20110049516A1

公开(公告)日：2011-03-03

申请号：US12941240

申请日：2010-11-08

申请人： William CHENG ,  Mirng-Ji Lii ,  Chen Yung Ching ,  Hsin-Hui Lee

发明人： William CHENG ,  Mirng-Ji Lii ,  Chen Yung Ching ,  Hsin-Hui Lee

IPC分类号： H01L23/544

CPC分类号： G06Q50/04 ,  Y02P90/30

摘要： A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type.

摘要翻译： 制造半导体晶片。 晶片具有多个管芯。 多个模具包括至少可操作的第一类型的可操作模具和不同于第一类型的第二类型的可操作模具。 第二类型的模具被使得不可操作，同时保持第一类型的模具可操作。 晶片在其上设置有第一类型的可操作模具和第二类型的不可操作模具，用于第一类型的模具的测试。

公开(公告)号：US07851272B2

公开(公告)日：2010-12-14

申请号：US11755461

申请日：2007-05-30

申请人： William Cheng ,  Mirng-Ji Lii ,  Chen Yung Ching ,  Hsin-Hui Lee

发明人： William Cheng ,  Mirng-Ji Lii ,  Chen Yung Ching ,  Hsin-Hui Lee

IPC分类号： H01L21/44

CPC分类号： G06Q50/04 ,  Y02P90/30

摘要： A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type.

摘要翻译： 制造半导体晶片。 晶片具有多个管芯。 多个模具包括至少可操作的第一类型的可操作模具和不同于第一类型的第二类型的可操作模具。 第二类型的模具被使得不可操作，同时保持第一类型的模具可操作。 晶片在其上设置有第一类型的可操作模具和第二类型的不可操作模具，用于第一类型的模具的测试。

公开(公告)号：US07772691B2

公开(公告)日：2010-08-10

申请号：US11871802

申请日：2007-10-12

申请人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Chien-Hsiun Lee

发明人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Chien-Hsiun Lee

IPC分类号： H01L23/10

CPC分类号： H01L23/4334 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/03

摘要： A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate.

摘要翻译： 形成封装结构的方法包括提供多个管芯; 将多个模具附接到散热板上; 以及将所述散热板锯切成多个封装，每个封装包括所述多个管芯中的一个和所述散热板的一个。

公开(公告)号：US20080142994A1

公开(公告)日：2008-06-19

申请号：US12036928

申请日：2008-02-25

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

IPC分类号： H01L23/52

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2924/013

摘要： A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

摘要翻译： 半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

公开(公告)号：US07256071B2

公开(公告)日：2007-08-14

申请号：US11420822

申请日：2006-05-30

申请人： Hsin-Hui Lee ,  Chao-Yuan Su

发明人： Hsin-Hui Lee ,  Chao-Yuan Su

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L23/13 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00

摘要： A substrate structure comprising a substrate; a solder mask is formed over the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern including openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.

摘要翻译： 一种衬底结构，包括衬底; 在衬底上形成焊料掩模; 以及形成在焊接掩模内的金属迹线结构。 金属迹线结构包括用于接收底部填充物的通道。 金属轨迹结构还包括具有从其向外辐射的臂的中心部分，将焊接掩模分成不同的区域。 一种底部填充芯片的方法，其中具有形成在芯片的下侧上的焊料凸块图案的芯片首先放置在本发明的金属迹线结构上。 焊料凸块图案包括在金属迹线结构上的开口。 底部填充物被引入到金属迹线结构中，使得底部填充物从金属迹线结构和焊料凸块之间流动，从而在芯片下面填充。

公开(公告)号：US20070087479A1

公开(公告)日：2007-04-19

申请号：US11610752

申请日：2006-12-14

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US20070007649A1

公开(公告)日：2007-01-11

申请号：US11160753

申请日：2005-07-07

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。