公开(公告)号：US20140225803A1

公开(公告)日：2014-08-14

申请号：US14170361

申请日：2014-01-31

申请人： Gerardo HUERTA ,  Jude LEE ,  John R. SANFORD ,  Gonzalo P. JABBAZ ,  Hsin-Ming CHEN ,  Robert PERA

发明人： Gerardo HUERTA ,  Jude LEE ,  John R. SANFORD ,  Gonzalo P. JABBAZ ,  Hsin-Ming CHEN ,  Robert PERA

IPC分类号： H01Q1/42 ,  H01Q21/00 ,  H01Q9/04

CPC分类号： H01Q1/428 ,  H01Q1/2291 ,  H01Q1/42 ,  H01Q3/08 ,  H01Q5/50 ,  H01Q9/0428 ,  H01Q21/0087 ,  H01Q21/065 ,  Y10T29/49018

摘要： Indoor/outdoor broadband wireless combined radio/antennas configured to include an integrated adjustable mount allowing mounting to a pole or stand and adjustment of the angle of the device (e.g., the altitude) by a lockable ball joint. The device may include a compact array antenna having a high gain configured to operate in, for example, the 5.15 to 5.85 GHz band and/or the 2.40-2.48 GHz band. The antenna emitters may be arranged in a separate plane from a plane containing the antenna feed connecting the emitting elements and also from a ground plane. The antenna array may be contained within a protective weatherproof housing along with the radio control circuitry. The antenna may be manufactured by a simple stamping/forming process. The apparatuses may be configured for low impedance mismatch and may have a high gain relative to a very small and compact overall shape.

摘要翻译： 室内/室外宽带无线组合无线电/天线被配置为包括集成的可调节安装座，其允许安装到杆或支架上并且通过可锁定的球窝接头来调节装置的角度（例如高度）。 该装置可以包括具有被配置为在例如5.15至5.85GHz频带和/或2.40-2.48GHz频带中操作的高增益的紧凑阵列天线。 天线发射器可以布置在与包含连接发射元件的天线馈电的平面以及从地平面的单独的平面中。 天线阵列可以与无线电控制电路一起被包含在保护性防水外壳内。 天线可以通过简单的冲压/成型工艺来制造。 这些装置可以被配置为用于低阻抗失配，并且相对于非常小且紧凑的总体形状可以具有高增益。

公开(公告)号：US20140225802A1

公开(公告)日：2014-08-14

申请号：US14170307

申请日：2014-01-31

申请人： Gerardo HUERTA ,  Jude LEE ,  Hsin-Ming CHEN ,  Robert PERA

发明人： Gerardo HUERTA ,  Jude LEE ,  Hsin-Ming CHEN ,  Robert PERA

IPC分类号： H01Q1/42

CPC分类号： H01Q1/428 ,  H01Q1/2291 ,  H01Q1/42 ,  H01Q3/08 ,  H01Q5/50 ,  H01Q9/0428 ,  H01Q21/0087 ,  H01Q21/065 ,  Y10T29/49018

摘要： Radio devices for wireless transmission including an integrated adjustable mount allowing mounting to a pole or stand and adjustment of the angle of the device (e.g., the altitude). The device may include a compact array antenna having a high gain configured to operate in, for example, the 5.15 to 5.85 GHz band and/or the 2.40-2.48 GHz band. The antenna emitters may be arranged in a separate plane from a plane containing the antenna feed connecting the emitting elements and also from a ground plane. The antenna array may be contained within a protective weatherproof housing along with the radio control circuitry.

摘要翻译： 用于无线传输的无线电设备，包括集成的可调安装座，允许安装到杆或支架上并调节设备的角度（例如高度）。 该装置可以包括具有被配置为在例如5.15至5.85GHz频带和/或2.40-2.48GHz频带中操作的高增益的紧凑阵列天线。 天线发射器可以布置在与包含连接发射元件的天线馈电的平面以及从地平面的单独的平面中。 天线阵列可以与无线电控制电路一起被包含在保护性防水外壳内。

公开(公告)号：US08705289B2

公开(公告)日：2014-04-22

申请号：US13344621

申请日：2012-01-06

申请人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/12

摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.

摘要翻译： 提供一种闪存装置。 闪存装置包括多个存储单元和多个编程电压控制发生器。 每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。 每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。 预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。 在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

公开(公告)号：US08661730B2

公开(公告)日：2014-03-04

申请号：US13464031

申请日：2012-05-04

申请人： Hsin-Ming Chen

发明人： Hsin-Ming Chen

IPC分类号： A01G9/02

CPC分类号： A01G9/02

摘要： The present invention provides a versatile flower container includes a base, a top cover, a carrying container placing on the top of top cover and a sensing device placing in the base, the carrying container has a concave space can be used to accommodate the sponge, floral and water, the sensing device includes an electronic control panel, two humidity detection rod, a number of lamps and speakers, the two humidity detection rods are through the top cover and inserting into the sponge in the concave space, thereby they can detect the humidity values of the sponge, the lamps and the speaker can be activated to produce light and sound and then generate warning effect when the humidity values are not enough in the carrying container.

摘要翻译： 本发明提供了一种通用的花卉容器，其包括底座，顶盖，放置在顶盖顶部的承载容器和放置在基座中的感测装置，承载容器具有凹形空间可用于容纳海绵， 花卉和水，感应装置包括一个电子控制面板，两个湿度检测杆，多个灯和扬声器，两个湿度检测棒通过顶盖并插入到凹陷空间中的海绵中，从而可以检测到 海绵的湿度值，灯和扬声器可以被激活以产生光和声，并且当携带容器中的湿度值不足时产生警告效果。

公开(公告)号：US08658495B2

公开(公告)日：2014-02-25

申请号：US13602404

申请日：2012-09-04

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L29/788

CPC分类号： H01L21/28 ,  H01L27/11558 ,  H01L27/1156 ,  H01L29/401

摘要： The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.

摘要翻译： 本发明提供一种制造可擦除可编程单多晶非易失性存储器的方法，包括以下步骤：在第一类型衬底中限定第一区域和第二区域; 在所述第一区域中形成第二类型井区域; 形成覆盖所述第一区域的表面的第一栅极氧化物层和第二栅极氧化物层，其中所述第二栅极氧化物层延伸到所述第二区域并邻近所述第二区域; 在第二区域中形成DDD区域; 在所述第二区域上方蚀刻所述第二栅极氧化物层的一部分; 形成覆盖所述第一和第二栅极氧化物层的两个多晶硅栅极; 以及限定所述DDD区域中的第二类型掺杂区域并限定所述第二类型阱区域中的第一类型掺杂区域。

公开(公告)号：US08638589B2

公开(公告)日：2014-01-28

申请号：US13366370

申请日：2012-02-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C16/04 ,  H01L29/788 ,  H01L29/66 ,  H01L23/52

CPC分类号： H01L21/28282 ,  G11C16/10 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.

摘要翻译： 提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。 存储单元的操作方法包括以下步骤。 在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。 编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是 设置在第二栅极和阱区域之间。

公开(公告)号：US20130242663A1

公开(公告)日：2013-09-19

申请号：US13418352

申请日：2012-03-13

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.

摘要翻译： 本发明提供一种非易失性存储装置。 非易失性存储装置包括多个存储单元和信号发生器。 存储单元被布置成阵列，并且每个存储单元具有控制栅极端子，浮动栅极，源极线端子，位线端子，所选择的栅极端子和字线端子。 信号发生器耦合到存储单元。 当非易失性存储器件执行编程操作时，信号发生器向存储器单元中的多个禁止的存储单元的控制栅极端提供编程信号。 其中编程信号是具有直流（DC）偏移电压的脉冲信号。

公开(公告)号：US08384155B2

公开(公告)日：2013-02-26

申请号：US11697070

申请日：2007-04-05

申请人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Ya-Chin King

发明人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Ya-Chin King

IPC分类号： H01L29/94

CPC分类号： G11C17/04 ,  G11C2216/26 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/94

摘要： A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.

摘要翻译： 本文提供了具有栅极，栅极介电层，源极区域，漏极区域，电容器电介质层和导电插塞的一次性可编程存储器单元。 栅介质层设置在基板上。 栅极设置在栅极电介质层上。 源极区域和漏极区域分别设置在栅极的侧面的基板中。 电容器介质层设置在源极区域上。 电容器介电层是电阻保护氧化物层或自对准的自对准硅化物阻挡层。 导电插头设置在电容器电介质层上。 导电插头用作电容器的第一电极，源区域用作电容器的第二电极。 一次性可编程存储器（OTP）单元通过使电容器介质层击穿而被编程。

公开(公告)号：US20120273860A1

公开(公告)日：2012-11-01

申请号：US13541755

申请日：2012-07-04

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： H01L27/06

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

公开(公告)号：US08199578B2

公开(公告)日：2012-06-12

申请号：US12792746

申请日：2010-06-03

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.

摘要翻译： 提供具有浮置栅晶体管，编程门和控制栅极的单多晶硅层非易失性存储器。 浮栅晶体管具有浮置栅极和隧穿介电层。 浮栅设置在基板上。 隧道介电层设置在浮置栅极和衬底之间。 编程栅极，控制栅极和擦除栅极分别设置在由隧道电介质层分离的浮置栅极下的衬底中。 因此，在编程操作和擦除操作期间，通过隧道介电层的不同区域注入和排出电荷，以增加非易失性存储器的可靠性。