公开(公告)号：US08198797B2

公开(公告)日：2012-06-12

申请号：US12446584

申请日：2007-10-18

申请人： Eiichi Iijima ,  Guo Hua Shen ,  Tohru Satake

发明人： Eiichi Iijima ,  Guo Hua Shen ,  Tohru Satake

IPC分类号： H01J29/46

CPC分类号： H01J37/07 ,  H01J3/026 ,  H01J37/06 ,  H01J37/304 ,  H01J2237/004 ,  H01J2237/182

摘要： [Object] In the control of electron beam focusing of a pierce-type electron gun, any influences from the space charge effect and space charge neutralizing action within the electron gun are eliminated to attain complete control of an electron beam.[Solving Means] Feedback control of the pressure within the electron gun is performed by directly measuring temperature at an internal of the pierce-type electron gun. It is desirable that locations where the direct measurement of the temperature at the internal of the electron gun is performed are an anode (39) and a flow register (43). Further, the direct measurement can be performed at any one of a ring, an aperture and an exhaust pipe provided at an outlet or an inlet of any one of a cathode chamber (31), an intermediate chamber, and a scanning chamber (33). Accordingly, all of stabilization of beam producing area (optimized design of electron gun itself), stabilization of beam transporting portion and stabilization of beam using portion have become appropriate.

摘要翻译： 目的在穿透型电子枪的电子束聚焦的控制中，消除了电子枪内的空间电荷效应和空间电荷中和作用的任何影响，以完全控制电子束。 [解决方法]电子枪内的压力的反馈控制通过直接测量穿孔式电子枪内部的温度来进行。 期望进行电子枪内部的温度的直接测量的位置是阳极（39）和流动寄存器（43）。 此外，直接测量可以在设置在阴极室（31），中间室和扫描室（33）中的任一个的出口或入口处的环，孔和排气管中的任一个处进行， 。 因此，射束产生区域的所有稳定（电子枪本身的优化设计），光束传送部分的稳定和光束使用部分的稳定已经变得合适。

公开(公告)号：US20100270143A1

公开(公告)日：2010-10-28

申请号：US12808045

申请日：2009-01-15

申请人： Yukio Kikuchi ,  Guo Hua Shen

发明人： Yukio Kikuchi ,  Guo Hua Shen

IPC分类号： C23C14/35

CPC分类号： H01F41/303 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  C23C14/351 ,  C23C14/352 ,  G01R33/09 ,  G01R33/098 ,  H01F7/0273 ,  H01F10/3254 ,  H01F10/3295 ,  H01J37/3266 ,  H01J37/34 ,  H01J37/3414 ,  H01L43/12

摘要： A substrate stage that is arranged in a vacuum chamber and that has a substrate mounting surface on which a substrate is mounted, including a first magnetic field applying unit that applies a magnetic field to the substrate, in which the internal magnetization direction of the first magnetic field applying unit and the thickness direction of the substrate match.

摘要翻译： 布置在真空室中并且具有其上安装有基板的基板安装表面的基板台，包括向基板施加磁场的第一磁场施加单元，其中第一磁体的内部磁化方向 场施加单元和衬底的厚度方向匹配。

公开(公告)号：US20090046466A1

公开(公告)日：2009-02-19

申请号：US12191387

申请日：2008-08-14

申请人： Ching-Fu Yang ,  Chich-Hua Shen ,  Lei-Wei Tseng

发明人： Ching-Fu Yang ,  Chich-Hua Shen ,  Lei-Wei Tseng

IPC分类号： F21V29/02

CPC分类号： F21V19/0035 ,  F21K9/00 ,  F21V29/717 ,  F21V29/76 ,  F21Y2115/10

摘要： A light emitting diode (LED) module is disclosed. The LED module includes a base, a LED component, a pressing piece, and a plurality of screws. The base has a top surface and a positioning hole on the top surface. The LED component has a bottom surface and includes a positioning protrusion on the bottom surface. Wherein after the LED component is disposed on the base, the positioning protrusion is coupled with the positioning hole to position the LED component at the base. A pin of the LED component is located between the pressing piece and the base. The screws are used to screw the pressing member on the base.

摘要翻译： 公开了一种发光二极管（LED）模块。 LED模块包括基座，LED部件，按压片和多个螺钉。 基座上表面有一个顶面和一个定位孔。 LED部件具有底面并且在底面上包括定位突起。 其中在LED部件设置在基座上之后，定位突起与定位孔耦合以将LED部件定位在基座处。 LED组件的一个引脚位于按压件和底座之间。 螺钉用于将按压构件拧在基座上。

公开(公告)号：US20090011131A1

公开(公告)日：2009-01-08

申请号：US12146475

申请日：2008-06-26

申请人： Yu-Cheng Chou ,  Te-Li Tsai ,  Ming-Feng Tsai ,  Chich-Hua Shen ,  Hsueh-Lung Cheng

发明人： Yu-Cheng Chou ,  Te-Li Tsai ,  Ming-Feng Tsai ,  Chich-Hua Shen ,  Hsueh-Lung Cheng

IPC分类号： B05D3/10 ,  B05D1/18

CPC分类号： H01L23/373 ,  C23C18/1208 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/127 ,  F28F19/02 ,  H01L21/4871 ,  H01L23/3735 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for treating the surface of the heat dissipation module is provided. The method includes the following steps. First, a heat dissipation module is provided. Next, a nano-material layer is formed on the surface of the heat dissipation module. Thus, the surface of the heat dissipation module is isolated from air and effectively prevented from being oxidized or polluted.

摘要翻译： 提供了一种处理散热模块表面的方法。 该方法包括以下步骤。 首先，提供散热模块。 接着，在散热模块的表面上形成纳米材料层。 因此，散热模块的表面与空气隔离并有效防止氧化或污染。

公开(公告)号：US20080308944A1

公开(公告)日：2008-12-18

申请号：US12135008

申请日：2008-06-06

申请人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

发明人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76808

摘要： Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

摘要翻译： 使用通孔插头消除负载效应的方法。 根据一个实施例，本发明提供了一种处理集成电路的方法，其中减小了负载效应。 该方法包括提供基板的步骤，其特征在于第一厚度。 该方法还包括用于形成覆盖基板的金属间介电层的停止。 金属间介电层的特征在于第二厚度。 该方法还包括用于形成覆盖金属间介电层的第一光致抗蚀剂层的步骤。 第一光致抗蚀剂层与第一图案相关联。 另外，该方法包括用于形成至少部分地位于金属间介电层内部的第一开口的步骤。 第一通孔开口的特征在于第一深度。 该方法还包括用于去除第一光致抗蚀剂层的步骤。 该方法还包括形成通孔塞的步骤。

公开(公告)号：US20050196917A1

公开(公告)日：2005-09-08

申请号：US10790786

申请日：2004-03-03

申请人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

发明人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  H01L27/10852

摘要： A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.

摘要翻译： 公开了一种形成具有（111）结构的高电容结晶介电层的方法。 在一个示例性实施例中，多个核的沉积在约430至460摄氏度范围内的温度下进行，随后在大于600摄氏度的温度下生长连续的BSTO介电层。 在示例性实施例中，公开了用于生长具有约30nm或更小的高电容和厚度的钡锶氧化钛膜的方法。

公开(公告)号：US06621325B2

公开(公告)日：2003-09-16

申请号：US09956203

申请日：2001-09-18

申请人： Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

发明人： Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

IPC分类号： H03K301

CPC分类号： H03K19/17792 ,  G06F17/5054 ,  H01L27/0928 ,  H01L27/11807

摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

摘要翻译： 用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。 用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。 在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。 在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

公开(公告)号：US06609600B1

公开(公告)日：2003-08-26

申请号：US10078507

申请日：2002-02-21

申请人： Chin Hua Shen

发明人： Chin Hua Shen

IPC分类号： F16D4700

CPC分类号： F16D43/18

摘要： A centrifugal clutch comprises a driving wheel, an operative disc connected to the driving wheel to move therewith, a transmission disc mounted to an outer periphery of the operative disc, a follower shaft, a friction mechanism, and a coupling device for releasable coupling with a gear train of a gearbox. The follower shaft extends through the driving wheel, the operative disc, and the transmission disc. The friction mechanism is fixed to the transmission disc and in frictional engagement with a friction portion of the driving wheel. When the driving wheel turns at an idling speed, the friction portion drives the friction mechanism, the transmission disc, and the follower shaft to turn slowly with a constant torque, thereby allowing easy gear shifting through the coupling device.

摘要翻译： 离心式离合器包括驱动轮，连接到驱动轮以与其一起移动的操作盘，安装到操作盘的外周的传动盘，从动轴，摩擦机构和用于可释放地联接的联接装置 齿轮箱的齿轮系。 从动轴延伸穿过驱动轮，操作盘和传动盘。 摩擦机构固定在传动盘上并与驱动轮的摩擦部摩擦接合。 当驱动轮以怠速转动时，摩擦部驱动摩擦机构，传动盘和从动轴以恒定的转矩缓慢转动，从而容易地通过联接装置进行换档。

公开(公告)号：US06420272B1

公开(公告)日：2002-07-16

申请号：US09460700

申请日：1999-12-14

申请人： Hua Shen ,  David Edward Kotecki ,  Satish D. Athavale ,  Jenny Lian ,  Gerhard Kunkel ,  Nimal Chaudhary

发明人： Hua Shen ,  David Edward Kotecki ,  Satish D. Athavale ,  Jenny Lian ,  Gerhard Kunkel ,  Nimal Chaudhary

IPC分类号： H01L2100

CPC分类号： H01L28/60 ,  H01L21/02071 ,  H01L21/31116 ,  H01L21/32139 ,  H01L28/55

摘要： In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode. A method of removing the hard mask material without damaging the surrounding surface includes the steps of: depositing a soft mask photoresist material over the composite surface, including the hard masked covered noble metal electrode and the dielectric surface, in a manner such that the soft mask material is thinner over the region of the noble metal electrode; removing the portion of the soft mask material over the noble metal electrode leaving the soft mask material over the dielectric surface; etching the hard mask material with the soft mask material protecting the dielectric surface; and removing the remaining portion of the soft mask material.

摘要翻译： 在使用高介电常数电介质材料形成的叠层电容器存储元件的半导体动态随机存取存储器电路中，典型的是使用贵金属电极形成叠层电容器。 通常，贵金属电极的蚀刻工艺需要使用诸如氧化硅的硬掩模图形材料。 去除这种硬掩模常常导致图案化的贵金属电极周围的电介质表面的损坏。 在不损坏周围表面的情况下去除硬掩模材料的方法包括以下步骤：在复合表面上沉积软掩模光致抗蚀剂材料，包括硬掩蔽的贵金属电极和电介质表面，使得软掩模 材料在贵金属电极的区域上较薄; 在所述贵金属电极上除去所述软掩模材料的所述部分，从而将所述软掩模材料留在所述电介质表面上; 用保护电介质表面的软掩模材料蚀刻硬掩模材料; 以及去除所述软掩模材料的剩余部分。

公开(公告)号：US06420267B1

公开(公告)日：2002-07-16

申请号：US09551757

申请日：2000-04-18

申请人： Chenting Lin ,  Ronald J. Schutz ,  Andreas Knorr ,  Keith Wong ,  Hua Shen ,  Jenny Lian

发明人： Chenting Lin ,  Ronald J. Schutz ,  Andreas Knorr ,  Keith Wong ,  Hua Shen ,  Jenny Lian

IPC分类号： H01L2100

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.

摘要翻译： 提供了一种形成用于层叠电容器的集成屏障/触点的方法，其导致所有权成本降低以及名义上比常规结构厚几倍的屏障。 与常规装置相比，所得结构导致接触插头电阻降低。