公开(公告)号：US08247277B2

公开(公告)日：2012-08-21

申请号：US13366269

申请日：2012-02-04

申请人： Huang-Chung Cheng ,  Ta-Chuan Liao ,  Sheng-Kai Chen ,  Ying-Hui Chen ,  Chi-Neng Mo

发明人： Huang-Chung Cheng ,  Ta-Chuan Liao ,  Sheng-Kai Chen ,  Ying-Hui Chen ,  Chi-Neng Mo

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78696 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a thin film transistor is provided. An insulating pattern layer having at least one protrusion is formed on a substrate. At least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. The spacer and the amorphous semiconductor patterns are crystallized. The protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. A carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.

摘要翻译： 提供了薄膜晶体管的制造方法。 在基板上形成具有至少一个突起的绝缘图案层。 在绝缘图案层上形成有至少一个间隔物和彼此分离的多个非晶半导体图案。 间隔件形成在突起的一侧并连接在非晶半导体图案之间。 间隔物和非晶半导体图案结晶。 去除间隔物下面的突起和绝缘图案层，从而形成具有多个拐角的束结构并悬挂在基底上。 顺序地形成载流子隧道层，载流子俘获层和载流子阻挡层，以柔顺包裹波束结构的角部。 此后，在基板上形成栅极以覆盖光束结构并包裹载流子阻挡层。

公开(公告)号：US20120135571A1

公开(公告)日：2012-05-31

申请号：US13366269

申请日：2012-02-04

申请人： Huang-Chung Cheng ,  Ta-Chuan Liao ,  Sheng-Kai Chen ,  Ying-Hui Chen ,  Chi-Neng Mo

发明人： Huang-Chung Cheng ,  Ta-Chuan Liao ,  Sheng-Kai Chen ,  Ying-Hui Chen ,  Chi-Neng Mo

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a thin film transistor is provided. An insulating pattern layer having at least one protrusion is formed on a substrate. At least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. The spacer and the amorphous semiconductor patterns are crystallized. The protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. A carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.

摘要翻译： 提供了薄膜晶体管的制造方法。 在基板上形成具有至少一个突起的绝缘图案层。 在绝缘图案层上形成有至少一个间隔物和彼此分离的多个非晶半导体图案。 间隔件形成在突起的一侧并连接在非晶半导体图案之间。 间隔物和非晶半导体图案结晶。 去除间隔物下面的突起和绝缘图案层，从而形成具有多个拐角的束结构并悬挂在基底上。 顺序地形成载流子隧道层，载流子俘获层和载流子阻挡层，以柔顺包裹波束结构的角部。 此后，在基板上形成栅极以覆盖光束结构并包裹载流子阻挡层。

公开(公告)号：US20100133544A1

公开(公告)日：2010-06-03

申请号：US12366657

申请日：2009-02-06

申请人： Ta-Chuan Liao ,  Huang-Chung Cheng ,  Ya-Hsiang Tai ,  Szu-Fen Chen

发明人： Ta-Chuan Liao ,  Huang-Chung Cheng ,  Ya-Hsiang Tai ,  Szu-Fen Chen

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/42384 ,  H01L29/66757

摘要： A thin film transistor (TFT) includes a poly-silicon island, a gate insulating layer, a gate stack layer, and a dielectric layer. The poly-silicon island includes a source region and a drain region. The gate insulating layer covers the poly-silicon island. The gate stack layer is disposed on the gate insulating layer and includes a first conductive layer and a second conductive layer. A length of the first conductive layer is less than a length of the second conductive layer. The dielectric layer covers the gate insulating layer and the gate stack layer, and therefore a number of cavities are formed between the second conductive layer and the gate insulating layer.

摘要翻译： 薄膜晶体管（TFT）包括多晶硅岛，栅极绝缘层，栅极堆叠层和电介质层。 多晶硅岛包括源极区和漏极区。 栅极绝缘层覆盖多晶硅岛。 栅极堆叠层设置在栅极绝缘层上，并且包括第一导电层和第二导电层。 第一导电层的长度小于第二导电层的长度。 电介质层覆盖栅极绝缘层和栅极堆叠层，因此在第二导电层和栅极绝缘层之间形成多个空腔。

公开(公告)号：US07413912B2

公开(公告)日：2008-08-19

申请号：US11126459

申请日：2005-05-11

申请人： Jyh-Shin Chen ,  Der-Chi Shye ,  Meng-Wei Kuo ,  Ming-Hua Shiao ,  Jiann-Shium Kao ,  Huang-Chung Cheng ,  Bi-Shiou Chiou

发明人： Jyh-Shin Chen ,  Der-Chi Shye ,  Meng-Wei Kuo ,  Ming-Hua Shiao ,  Jiann-Shium Kao ,  Huang-Chung Cheng ,  Bi-Shiou Chiou

IPC分类号： H01L21/00

CPC分类号： H01C7/008 ,  H01C7/025 ,  H01L27/016

摘要： A microsensor fabricated with a ferroelectric material and a fabrication method therefor are provided. The microsensor includes a support, an insulating layer on the support, a first electrode on the insulating layer, a ferroelectric layer having at least a metal on the insulating layer and the first electrode, and at least a second electrode on the ferroelectric layer.

摘要翻译： 提供了一种用铁电材料制造的微型传感器及其制造方法。 微传感器包括支撑体，支撑体上的绝缘层，绝缘层上的第一电极，绝缘层上至少有金属的铁电层和第一电极，以及铁电层上的至少第二电极。

公开(公告)号：US20070159442A1

公开(公告)日：2007-07-12

申请号：US11306813

申请日：2006-01-12

申请人： Huang-Chung Cheng ,  Ya-Hsiang Tai ,  Bo-Ting Chen ,  Chun-Hsiang Fang

发明人： Huang-Chung Cheng ,  Ya-Hsiang Tai ,  Bo-Ting Chen ,  Chun-Hsiang Fang

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/02

摘要： An analog output buffer circuit for a flat panel display is provided for improving an output signal distortion. The circuit includes a transistor, a current source, an input capacitor, an upper switch, a lower switch, a first switch, a second switch and a third switch. In which, the transistor and the current source are electrically connected in series between a first power supply and a second power supply. The current source provides a compensatory current for the transistor when a leakage current occurs. The upper switch and the first switch are turned on during the first period, and the lower switch and the second switch are turn on during the second period, in which the second period is after the first period. Those switches eliminate the drawback of different voltage levels between the input signal and the output signal obtained from the output buffer circuit inputted by the input signal.

摘要翻译： 提供了一种用于平板显示器的模拟输出缓冲电路，用于改善输出信号失真。 电路包括晶体管，电流源，输入电容器，上开关，下开关，第一开关，第二开关和第三开关。 其中，晶体管和电流源串联电连接在第一电源和第二电源之间。 当发生漏电流时，电流源为晶体管提供补偿电流。 上部开关和第一开关在第一时段期间导通，并且下部开关和第二开关在第二时段期间接通，其中第二周期在第一周期之后。 这些开关消除了输入信号与从输入信号输入的输出缓冲电路获得的输出信号之间的不同电压电平的缺点。

公开(公告)号：US06975371B2

公开(公告)日：2005-12-13

申请号：US10701637

申请日：2003-11-06

申请人： Zon-Zer Yu ,  Dong-Yuan Goang ,  Huang-Chung Cheng

发明人： Zon-Zer Yu ,  Dong-Yuan Goang ,  Huang-Chung Cheng

IPC分类号： G02F1/1335 ,  G02F1/13357 ,  G02F1/1368 ,  G02F1/1333 ,  H01L21/00

CPC分类号： G02F1/133603 ,  G02F1/1368 ,  G02F2001/133565

摘要： A structure of an organic light-emitting TFT LCD and the method for making the same are disclosed. The invention provides a glass substrate on which a TFT IC is formed. A metal layer forms the top layer of the TFT. Afterwards, a white light-emitting organic material layer is deposited thereon. A cover layer is then used to flatten the surface of the organic material layer. Finally, a photo mask pattern and a color filter plate are formed, completing the assembly of the TFT LCD.

摘要翻译： 公开了有机发光TFT LCD的结构及其制造方法。 本发明提供一种其上形成有TFT IC的玻璃基板。 金属层形成TFT的顶层。 之后，在其上沉积白色发光有机材料层。 然后使用覆盖层来平坦化有机材料层的表面。 最后，形成光掩膜图案和滤色片，完成TFT LCD的组装。

公开(公告)号：US06423618B1

公开(公告)日：2002-07-23

申请号：US09461869

申请日：1999-12-15

申请人： Ming-Jang Lin ,  Chorng-Wei Liaw ,  Tian-Fure Shiue ,  Ching-Hsiang Hsu ,  Huang-Chung Cheng

发明人： Ming-Jang Lin ,  Chorng-Wei Liaw ,  Tian-Fure Shiue ,  Ching-Hsiang Hsu ,  Huang-Chung Cheng

IPC分类号： H01L21302

CPC分类号： H01L29/66621 ,  H01L29/7834

摘要： A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench. Portions of the fourth dielectric layer and the polysilicon layer are removed until the surfaces of the fourth dielectric layer and the polysilicon layer are substantially level with the surface of the base region.

摘要翻译： 一种用于制造功率金属氧化物半导体场效应晶体管的沟槽栅极结构的方法。 提供了一种衬底，该衬底在其上具有外延层，形成在外延层中的基极区域，形成在该基极区域的一部分中的源极区域，在该基极区域上的第一介电层和源极区域，第二电介质层 并且穿过第二介电层和第一介电层，源极区域和基极区域并进入外延层的沟槽。 第三电介质层形成在沟槽的底部。 在沟槽中形成保形栅极氧化层。 在第二电介质层和沟槽中形成共形多晶硅层。 在多晶硅层上形成第四电介质层以填充沟槽。 去除第四电介质层和多晶硅层的部分，直到第四电介质层和多晶硅层的表面与基极区域的表面基本平齐。

公开(公告)号：US06259618B1

公开(公告)日：2001-07-10

申请号：US09563586

申请日：2000-05-03

申请人： Chorng-Wei Liaw ,  Hau-Luen Tien ,  Wei-Jye Lin ,  Ming-Jang Lin ,  Tian-Fure Shiue ,  Huang-Chung Cheng ,  Ching-Hsiang Hsu

发明人： Chorng-Wei Liaw ,  Hau-Luen Tien ,  Wei-Jye Lin ,  Ming-Jang Lin ,  Tian-Fure Shiue ,  Huang-Chung Cheng ,  Ching-Hsiang Hsu

IPC分类号： H02M100

CPC分类号： H01L29/7808 ,  H01L27/085 ,  H01L29/7802 ,  H01L29/7815 ,  H02M1/36 ,  H02M3/33507 ,  H03K17/04206 ,  H03K17/0822

摘要： A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.

摘要翻译： 用于切换模式电源的功率芯片包括高压芯片和控制单元芯片。 高电压芯片包含在来自控制单元的输出信号的控制下导通/截止的开关功率金属氧化物半导体（MOS）晶体管，以及耦合在开关电源的漏极之间的结型场效应晶体管（JFET） MOS晶体管和控制单元的电源端子用作用于在启动期间驱动控制单元的启动元件，其中JFET具有负阈值电压，并且其绝对值等于用于驱动控制单元的电压。 高电压芯片中的JFET结构还包括用于控制单元的过电压保护的齐纳二极管。 高电压晶片还包含与用于检测开关功率MOS晶体管的漏极电流的开关功率MOS晶体管的漏极耦合的电流检测功率MOS晶体管。 芯片组可以封装成电源模块。

公开(公告)号：US06255203B1

公开(公告)日：2001-07-03

申请号：US09216672

申请日：1998-12-16

申请人： Huang-Chung Cheng ,  Wen-Koi Lai ,  Nan-Ching Chen

发明人： Huang-Chung Cheng ,  Wen-Koi Lai ,  Nan-Ching Chen

IPC分类号： H01L2120

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L29/4933

摘要： This application relates to a process to suppress the impurity diffusion through gate oxide on silicided amorphous-Si gate structures that utilize the silicide layers as the implantation barrier to minimize the impurity diffusion by reducing the projectile range and implant-induced defects, resulting in smaller flat-band voltage(VFB) shift and better characteristics of the breakdown field(Ebd) and charge to breakdown(Qbd). In addition, the amorphous-Si underlying layer is simultaneously kept during the formation of a low-temperature self-aligned silicide (SAD) process to further retard the impurity diffusion. Hence, the usage of such bilayered silicide/amorphous-Si films could effectively retard the impurity diffusion, by combining both effects of the amorphous-Si layer and the silicide process or inducing other undesirable effects such as the increase of gate sheet resistance.

摘要翻译： 本申请涉及一种通过硅化非晶Si栅极结构抑制杂质扩散的方法，其利用硅化物层作为注入势垒，通过减少抛射体范围和植入物引起的缺陷来最小化杂质扩散，导致较小的平面 带状电压（VFB）偏移和更好的击穿场（Ebd）特性和击穿电荷（Qbd）。 此外，在形成低温自对准硅化物（SAD）工艺期间，同时保持非晶Si下层，以进一步延缓杂质扩散。 因此，这种双层硅化物/非晶硅膜的使用可以通过组合非晶硅层和硅化物工艺的两种效应或引起其他不期望的影响，例如增加栅极薄层电阻，来有效地延缓杂质扩散。

公开(公告)号：US20130009144A1

公开(公告)日：2013-01-10

申请号：US13286902

申请日：2011-11-01

申请人： Huang-Chung CHENG ,  Yu-Chih HUANG ,  Po-Yu YANG ,  Shin-Chuan CHIANG ,  Huai-An LI

发明人： Huang-Chung CHENG ,  Yu-Chih HUANG ,  Po-Yu YANG ,  Shin-Chuan CHIANG ,  Huai-An LI

IPC分类号： H01L29/24

CPC分类号： H01L29/78603 ,  H01L27/1225 ,  H01L29/78606 ,  H01L29/7869

摘要： A top-gate transistor array substrate includes a transparent substrate with a plane, an ion release layer, a pixel array, and a first insulating layer. The ion release layer is disposed on the transparent substrate and completely covers the plane. The pixel array is disposed on the ion release layer and includes a plurality of transistors and a plurality of pixel electrodes. Each of the transistors includes a source, a drain, a gate and a MOS (metal oxide semiconductor) layer. The drain, the source and the MOS layer are disposed on the ion release layer. The pixel electrodes are electrically connected to the drains respectively. The gate is disposed above the MOS layer. The first insulating layer is disposed between the MOS layers and the gates. The MOS layer contacts the ion release layer. The ion release layer can release a plurality of ions into the MOS layers.

摘要翻译： 顶栅晶体管阵列基板包括具有平面的透明基板，离子剥离层，像素阵列和第一绝缘层。 离子剥离层设置在透明基板上并完全覆盖平面。 像素阵列设置在离子剥离层上，并且包括多个晶体管和多个像素电极。 每个晶体管包括源极，漏极，栅极和MOS（金属氧化物半导体）层。 漏极，源极和MOS层设置在离子剥离层上。 像素电极分别与漏极电连接。 栅极设置在MOS层的上方。 第一绝缘层设置在MOS层和栅极之间。 MOS层与离子释放层接触。 离子剥离层可以将多个离子释放到MOS层中。