公开(公告)号：US08324675B2

公开(公告)日：2012-12-04

申请号：US12644976

申请日：2009-12-22

申请人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

发明人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region.

摘要翻译： 一种具有垂直通道结构的闪速存储器件。 闪速存储装置包括：具有沿第一方向延伸的表面的基板，具有柱状的沟道区域，并且在与第一方向垂直的第二方向上从基板延伸;栅极介电层，形成在沟道区域周围 ，包括在所述第二方向上依次形成在所述沟道区周围的多个晶体管的存储单元串，其中所述栅介质层设置在所述多个晶体管和所述沟道区之间，并且位线连接到所述多个晶体管中的一个晶体管 并且围绕通道区域的一端的侧壁和上表面，以便直接接触通道区域。

公开(公告)号：US20110024816A1

公开(公告)日：2011-02-03

申请号：US12644976

申请日：2009-12-22

申请人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

发明人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region.

摘要翻译： 一种具有垂直通道结构的闪速存储器件。 闪速存储装置包括：具有沿第一方向延伸的表面的基板，具有柱状的沟道区域，并且在与第一方向垂直的第二方向上从基板延伸;栅极介电层，形成在沟道区域周围 ，包括在所述第二方向上依次形成在所述沟道区周围的多个晶体管的存储单元串，其中所述栅介质层设置在所述多个晶体管和所述沟道区之间，并且位线连接到所述多个晶体管中的一个晶体管 并且围绕通道区域的一端的侧壁和上表面，以便直接接触通道区域。

公开(公告)号：US08836020B2

公开(公告)日：2014-09-16

申请号：US13285291

申请日：2011-10-31

申请人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

发明人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC分类号： H01L27/108 ,  G11C5/02 ,  G11C5/06 ,  H01L27/115 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

摘要翻译： 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。

公开(公告)号：US08729622B2

公开(公告)日：2014-05-20

申请号：US13276682

申请日：2011-10-19

申请人： Hui-Chang Moon ,  Sung-Min Hwang ,  Woonkyung Lee

发明人： Hui-Chang Moon ,  Sung-Min Hwang ,  Woonkyung Lee

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

摘要翻译： 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。

公开(公告)号：US20120256253A1

公开(公告)日：2012-10-11

申请号：US13432485

申请日：2012-03-28

申请人： Sung-Min Hwang ,  Woon-Kyung Lee ,  Young-Jin Kwon ,  Tae-Hee Lee ,  Hui-Chang Moon

发明人： Sung-Min Hwang ,  Woon-Kyung Lee ,  Young-Jin Kwon ,  Tae-Hee Lee ,  Hui-Chang Moon

IPC分类号： H01L29/78

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7827

摘要： Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad.

摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线，串选择线（SSL），焊盘和蚀刻停止层。 通道在基板上沿第一方向延伸。 通道包括杂质区，第一方向垂直于衬底的顶表面。 至少一个GSL，多个字线和至少一个SSL在信道的侧壁上沿第一方向彼此间隔开。 衬垫设置在通道的顶表面上。 蚀刻停止层接触焊盘。

公开(公告)号：US20120193705A1

公开(公告)日：2012-08-02

申请号：US13285291

申请日：2011-10-31

申请人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

发明人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC分类号： H01L29/78 ,  H01L23/48

CPC分类号： G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

摘要翻译： 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。

公开(公告)号：US20120098049A1

公开(公告)日：2012-04-26

申请号：US13276682

申请日：2011-10-19

申请人： Hui-Chang MOON ,  Sung-Min Hwang ,  Woonkyung Lee

发明人： Hui-Chang MOON ,  Sung-Min Hwang ,  Woonkyung Lee

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

摘要翻译： 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。