公开(公告)号：US20120113559A1

公开(公告)日：2012-05-10

申请号：US13288743

申请日：2011-11-03

Applicant: Hung T. Nguyen ,  George Tzeng ,  Daniel I. Handjojo ,  Paul Bocian ,  Matthias Brunner ,  Bernhard G. Mueller

Inventor： Hung T. Nguyen ,  George Tzeng ,  Daniel I. Handjojo ,  Paul Bocian ,  Matthias Brunner ,  Bernhard G. Mueller

IPC: H05F3/00

CPC classification number: H01L21/67748 ,  H01L21/6831 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention relate to methods and apparatus for minimizing electrostatic discharge in processing and testing systems utilizing large area substrates in the production of flat panel displays, solar panels, and the like. In one embodiment, an apparatus is described. The apparatus includes a testing chamber, a substrate support disposed in the testing chamber, the substrate support having a substrate support surface, a structure disposed in the testing chamber, the structure having a length that spans a width of the substrate support surface, the structure being linearly movable relative to the substrate support, and a brush device having a plurality of conductive bristles coupled to the structure and spaced a distance away from the substrate support surface of the substrate support, the brush device electrically coupling the support surface to ground through the structure.

Abstract translation: 本发明的实施例涉及在平板显示器，太阳能电池板等的生产中利用大面积基板的处理和测试系统中的静电放电最小化的方法和装置。 在一个实施例中，描述了一种装置。 该装置包括测试室，设置在测试室中的衬底支撑件，衬底支撑件具有衬底支撑表面，设置在测试室中的结构，该结构具有跨过衬底支撑表面的宽度的长度，该结构 相对于衬底支撑件可线性移动;以及刷子装置，其具有耦合到该结构并且离开衬底支撑件的衬底支撑表面间隔一定距离的多个导电刷毛，刷装置通过 结构体。

公开(公告)号：US08146314B2

公开(公告)日：2012-04-03

申请号：US11708570

申请日：2007-02-21

Applicant: Hung T. Nguyen

Inventor： Hung T. Nguyen

IPC: E04B2/72 ,  E04B2/58

CPC classification number: E04B1/14 ,  E04B1/08 ,  E04C2/08

Abstract: The prefabricated universal structural steel panel and panel system includes a generally elongated rectangular panel having an opposed exterior and interior surfaces, an opposed first and second end portions, and an opposed first and second side edge portions. At least two stiffening ribs are integrally formed in the panel and extend longitudinally between the first and second end portions. The first side edge portion has a beveled configuration and is integrally connected to an elongated male connecting member. An elongated female connecting member is integrally connected to the second side edge portion and extends adjacent the interior surface to define a fold. The elongated male connecting member of one panel is cooperatively profiled to mate with the female connecting member of an adjacent panel.

Abstract translation: 预制的通用结构钢板和面板系统包括具有相对的外表面和内表面的相当长的矩形面板，相对的第一和第二端部以及相对的第一和第二侧边缘部分。 至少两个加强肋一体地形成在面板中并在第一和第二端部之间纵向延伸。 第一侧边缘部分具有斜面构造并且与细长的阳连接构件一体地连接。 细长的阴连接构件一体地连接到第二侧边缘部分并且在内表面附近延伸以限定折叠。 一个面板的细长阳连接构件配合成型以与相邻面板的阴连接构件相配合。

公开(公告)号：US07330021B2

公开(公告)日：2008-02-12

申请号：US11018236

申请日：2004-12-21

Applicant: Shinichi Kurita ,  Emanuel Beer ,  Hung T. Nguyen ,  Benjamin Johnston ,  Fayez E. Abboud

Inventor： Shinichi Kurita ,  Emanuel Beer ,  Hung T. Nguyen ,  Benjamin Johnston ,  Fayez E. Abboud

IPC: G01R13/04

CPC classification number: G09G3/006 ,  G01R31/2893 ,  G01R31/305

Abstract: A substrate table and method for supporting and transferring a substrate are provided. The substrate table includes a segmented stage having an upper surface for supporting a substrate, and an end effector. The end effector includes two or more spaced apart fingers and an upper surface for supporting a substrate. The end effector is at least partially disposed and moveable within the segmented stage such that the fingers of the end effector and the segmented stage interdigitate to occupy the same horizontal plane. The segmented stage is adapted to raise and lower about the end effector.

Abstract translation: 提供了用于支撑和转移衬底的衬底台和方法。 衬底台包括具有用于支撑衬底的上表面的分段段和端部执行器。 末端执行器包括两个或更多间隔开的指状物和用于支撑基底的上表面。 末端执行器至少部分地设置并在分段台内移动，使得末端执行器和分段台阶的指状物相互指向以占据相同的水平面。 分段段适于围绕末端执行器升高和降低。

公开(公告)号：US07231510B1

公开(公告)日：2007-06-12

申请号：US10007498

申请日：2001-11-13

Applicant: Hung T. Nguyen ,  Shannon A. Wichman

Inventor： Hung T. Nguyen ,  Shannon A. Wichman

IPC: G06F7/483

CPC classification number: G06F7/5443 ,  G06F2207/3884

Abstract: A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue architecture, and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism including: (1) a multiply-accumulate unit (MAC) having an initial multiply stage and a subsequent accumulate stage and (2) out-of-order completion logic, associated with the MAC, that causes interim results produced by the multiply stage to be stored when the accumulate stage is unavailable and allows younger instructions to complete before the multiply-accumulate instructions.

Abstract translation: 一种用于处理具有至少四个宽度的指令问题架构的处理器的流水线中的无序完成处理多重累加指令的机制和方法，以及数字信号处理器（DSP） 机制或方法。 在一个实施例中，该机制包括：（1）具有初始乘法级和后续累加级的乘法累积单元（MAC），以及（2）与MAC相关联的无序完成逻辑，其导致中间结果 在累加阶段不可用时由乘法级产生，并允许较少的指令在乘法累加指令之前完成。

公开(公告)号：US07167939B2

公开(公告)日：2007-01-23

申请号：US10911798

申请日：2004-08-05

Applicant: Hung T. Nguyen ,  Keith D. Dang

Inventor： Hung T. Nguyen ,  Keith D. Dang

IPC: G06F13/368 ,  G06F3/00 ,  G06F13/14 ,  G06F11/00

CPC classification number: G06F13/4004

Abstract: A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transactions, initiated by a system device coupled to the global bus, that require access to a local device coupled to the local bus and a global bus adapter for handling transactions, initiated by a local device coupled to the local bus, that require access to a system device coupled to the system bus. The local bus adapter is further configured to issue signals which prevent the global bus adapter from handling transactions initiated by local devices coupled to the local bus while transactions initiated by system devices coupled to the global bus are on-going.

Abstract translation: 具有分层总线结构的计算机系统，其允许本地总线与其全局总线的去耦合。 通过使用异步系统总线适配器来实现本地总线的去耦，该异步系统总线适配器包括用于处理由耦合到全局总线的系统设备启动的事务的本地总线适配器，其需要访问耦合到本地总线的本地设备和 用于处理由耦合到本地总线的本地设备启动的事务的全局总线适配器，其需要访问耦合到系统总线的系统设备。 本地总线适配器还被配置为发出信号，其阻止全局总线适配器处理由耦合到本地总线的本地设备发起的事务，同时由耦合到全局总线的系统设备发起的事务正在进行。

公开(公告)号：US07085916B1

公开(公告)日：2006-08-01

申请号：US10066150

申请日：2001-10-26

Applicant: Hung T. Nguyen

Inventor： Hung T. Nguyen

IPC: G06F9/00

CPC classification number: G06F9/3804 ,  G06F9/381

Abstract: For use in a processor having an external memory interface, an instruction prefetch mechanism, a method of prefetching instructions and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a branch predictor that predicts whether a branch is to be taken, (2) prefetch circuitry, coupled to the branch predictor, that prefetches instructions associated with the branch via the external memory interface if the branch is taken and prefetches sequential instructions via the external memory interface if the branch is not taken and (3) a loop recognizer, coupled to the prefetch circuitry, that determines whether a loop is present in fetched instructions and reinstates a validity of instructions in the loop and prevents the prefetch circuitry from prefetching instructions outside of the loop until the loop completes execution.

Abstract translation: 用于具有外部存储器接口的处理器，指令预取机制，预取指令的方法和结合该机制或方法的数字信号处理器。 在一个实施例中，该机制包括：（1）预测是否要采用分支的分支预测器，（2）耦合到分支预测器的预取电路，其通过外部存储器接口预取与分支相关联的指令，如果 如果不采用分支，则分支被取出并通过外部存储器接口预取顺序指令，以及（3）耦合到预取电路的环路识别器，其确定获取的指令中是否存在循环并且恢复指令的有效性 循环并防止预取电路从环路外部预取指令，直到循环完成执行。

公开(公告)号：US07051146B2

公开(公告)日：2006-05-23

申请号：US10603303

申请日：2003-06-25

Applicant: Hung T. Nguyen ,  Shannon A. Wichman

Inventor： Hung T. Nguyen ,  Shannon A. Wichman

IPC: G06F13/14

CPC classification number: G06F9/30145 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3824 ,  G06F9/3885

Abstract: A processor is disclosed that executes an instruction including a user-defined value (an address or a command) and provides the user-defined value during execution of the instruction. In one embodiment the processor includes a bus interface adapted for coupling to a bus, and the processor drives the user-defined address or command upon one or more signal lines of the bus via the bus interface during execution of the instruction. A described data processing system includes the processor coupled to a device including an addressable register. The device receives a user-defined address from the processor and accesses the addressable register in response to the user-defined address. Methods are disclosed for obtaining a value stored in an addressable register, providing a value stored in an addressable register, storing a value in an addressable register, and modifying a value stored in an addressable register.

Abstract translation: 公开了一种处理器，其执行包括用户定义值（地址或命令）的指令，并在执行指令期间提供用户定义的值。 在一个实施例中，处理器包括适于耦合到总线的总线接口，并且处理器在执行指令期间经由总线接口在总线的一个或多个信号线上驱动用户定义的地址或命令。 所描述的数据处理系统包括耦合到包括可寻址寄存器的设备的处理器。 设备从处理器接收用户定义的地址，并响应于用户定义的地址访问可寻址寄存器。 公开了用于获得存储在可寻址寄存器中的值的方法，提供存储在可寻址寄存器中的值，将值存储在可寻址寄存器中，以及修改存储在可寻址寄存器中的值。

公开(公告)号：US06976156B1

公开(公告)日：2005-12-13

申请号：US10047515

申请日：2001-10-26

Applicant: Hung T. Nguyen

Inventor： Hung T. Nguyen

IPC: G06F9/38

CPC classification number: G06F9/3863 ,  G06F9/30145 ,  G06F9/3846 ,  G06F9/3853

Abstract: For use in a wide-issue pipelined processor, a mechanism for, and method of, reducing pipeline stalls between conditional branches and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a mispredict program counter (PC) generator that generates a mispredict PC value for each conditional branch instruction in a pipeline of the processor and (2) mispredict PC storage, coupled to the mispredict PC generator, that stores the mispredict PC value at least until a resolution of the conditional branch instruction occurs and makes the mispredict PC value available to a PC of the processor if the resolution results in a mispredict condition. The mispredict PC storage includes a mispredict PC queue and a number of staging registers wherein the mispredict PC queue has at least as many stages as the number of staging registers.

Abstract translation: 用于广泛问题的流水线处理器，减少条件分支与包含该机制或方法的数字信号处理器（DSP）之间的流水线停顿的机制和方法。 在一个实施例中，该机制包括：（1）错误预测的程序计数器（PC）生成器，其在处理器流水线中为每个条件转移指令生成错误的PC值，以及（2）错误地将PC存储器连接到错误的PC生成器 ，其存储错误的PC值至少直到发生条件分支指令的分辨率，并且如果分辨率导致错误的预测条件，则使错误的PC值可用于处理器的PC。 错误的PC存储包括错误的PC队列和多个分段寄存器，其中错误的PC队列具有至少与分段寄存器的数量相同的级数。

公开(公告)号：US06824343B2

公开(公告)日：2004-11-30

申请号：US10084762

申请日：2002-02-22

Applicant: Shinichi Kurita ,  Wendell T. Blonigan ,  Suhail Anwar ,  Toshio Kiyotake ,  Hung T. Nguyen

Inventor： Shinichi Kurita ,  Wendell T. Blonigan ,  Suhail Anwar ,  Toshio Kiyotake ,  Hung T. Nguyen

IPC: B65G4724

CPC classification number: H01L21/68 ,  H01L21/68728 ,  H01L21/68778 ,  H01L21/68792 ,  Y10S414/136 ,  Y10S414/139 ,  Y10S414/141

Abstract: A method and apparatus for supporting a substrate is generally provided. In one aspect, an apparatus for supporting a substrate includes a support plate having a first body disposed proximate thereto. A first pushing member is radially coupled to the first body and adapted to urge the substrate in a first direction parallel to the support plate when the first body rotates. In another aspect, a load lock chamber having a substrate support that supports a substrate placed thereon includes a cooling plate that is moved to actuate at least one alignment mechanism. The alignment mechanism includes a pushing member that urges the substrate in a first direction towards a center of the support. The pushing member may additionally rotate about an axis perpendicular to the first direction.

Abstract translation: 通常提供用于支撑衬底的方法和装置。 在一个方面，一种用于支撑衬底的装置包括具有靠近其设置的第一主体的支撑板。 第一推动构件径向耦合到第一主体并且适于在第一主体旋转时沿平行于支撑板的第一方向推动基板。 在另一方面，具有支撑其上放置的基板的基板支撑件的装载锁定室包括移动以致动至少一个对准机构的冷却板。 对准机构包括推动构件，其沿朝向支撑件的中心的第一方向推动基板。 推动构件可以另外围绕垂直于第一方向的轴旋转。

公开(公告)号：US06715038B1

公开(公告)日：2004-03-30

申请号：US09993431

申请日：2001-11-05

Applicant: Hung T. Nguyen ,  Mark A. Boike

Inventor： Hung T. Nguyen ,  Mark A. Boike

IPC: G06F1300

CPC classification number: G06F12/08 ,  G06F12/0875 ,  G06F12/0891

Abstract: For use in a processor having an instruction cache, an instruction memory and an external synchronous memory, a memory management mechanism, a method of managing memory and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes an external memory request abort circuit coupled to the external synchronous memory and an instruction cache invalidator associated with the external memory request abort circuit. In this embodiment, the external memory request abort circuit aborts a request to load an instruction from the external synchronous memory before the information is loaded into the instruction cache. Additionally, the instruction cache invalidator invalidates the instruction cache when address spaces of the instruction memory and the external synchronous memory overlap and the processor switches between the instruction memory and the external synchronous memory.

Abstract translation: 用于具有指令高速缓存，指令存储器和外部同步存储器的处理器，存储器管理机制，管理存储器的方法和结合该机构或方法的数字信号处理器。 在一个实施例中，该机制包括耦合到外部同步存储器的外部存储器请求中止电路和与外部存储器请求中止电路相关联的指令高速缓存无效器。 在本实施例中，在将信息加载到指令高速缓存器之前，外部存储器请求中止电路中止从外部同步存储器加载指令的请求。 此外，当指令存储器和外部同步存储器的地址空间重叠并且处理器在指令存储器和外部同步存储器之间切换时，指令高速缓存无效器使指令高速缓存失效。