公开(公告)号：US07897463B2

公开(公告)日：2011-03-01

申请号：US12651688

申请日：2010-01-04

Applicant: Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Hye-Jin Cho

Inventor： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Hye-Jin Cho

IPC: H01L21/336

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/66666 ,  H01L29/7831

Abstract: A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.

Abstract translation: 晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。 相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。 相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。 相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。 栅电极设置在第一和第二栅极绝缘体之间。 第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

公开(公告)号：US07768070B2

公开(公告)日：2010-08-03

申请号：US11832589

申请日：2007-08-01

Applicant: Eun-Jung Yun ,  Hye-Jin Cho ,  Dong-Won Kim ,  Sung-Min Kim

Inventor： Eun-Jung Yun ,  Hye-Jin Cho ,  Dong-Won Kim ,  Sung-Min Kim

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Abstract translation: 一种具有场效应晶体管的半导体器件及其制造方法。 通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。 原位掺杂的外延图案贯穿整个杂质浓度。 因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。 结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

公开(公告)号：US07675105B2

公开(公告)日：2010-03-09

申请号：US11376518

申请日：2006-03-15

Applicant: Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

Inventor： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract translation: 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US20090315094A1

公开(公告)日：2009-12-24

申请号：US12437773

申请日：2009-05-08

Applicant: Jong-Ho Lim ,  Choong-Ho Lee ,  Hye-Jin Cho

Inventor： Jong-Ho Lim ,  Choong-Ho Lee ,  Hye-Jin Cho

IPC: H01L29/788

CPC classification number: H01L27/11551

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

Abstract translation: 具有三维结构的非易失性存储装置。 非易失性存储器件包括多个堆叠的半导体层和形成在多个半导体层中的每一个上并且串联连接的多个存储单元晶体管。 配置在不同的半导体层上的存储单元晶体管被串联连接以包括在多个半导体层中形成电流路径的一个单元串，串联连接到单元串的一个边缘部分的第一选择晶体管和串联连接到单元串的第二选择晶体管 单元格串的其他边缘部分。

公开(公告)号：US20080081125A1

公开(公告)日：2008-04-03

申请号：US11902486

申请日：2007-09-21

Applicant: Hyun-Chul Jung ,  Jae-Woo Joung ,  Hye-Jin Cho ,  Yoon-Ah Baik ,  Sung-Il Oh

Inventor： Hyun-Chul Jung ,  Jae-Woo Joung ,  Hye-Jin Cho ,  Yoon-Ah Baik ,  Sung-Il Oh

IPC: C23C18/00 ,  H05H1/00

CPC classification number: H05K3/28 ,  H05K3/0091 ,  H05K2203/013

Abstract: A method for manufacturing cover lay of printed circuit board is disclosed. With a method that includes preparing a board on which a circuit pattern is formed, and jetting a protecting ink selectively on the board by inkjet printing, a cover lay of a complicated shape may be formed easily with high accuracy and high productivity, as a polymer ink is jetted by inkjet printing to form the cover lay for a flexible circuit board.

Abstract translation: 公开了印刷电路板盖板的制造方法。 通过包括制备在其上形成电路图案的板并且通过喷墨印刷在板上选择性地喷射保护油墨的方法，可以以高精度和高生产率容易地形成复杂形状的盖板作为聚合物 通过喷墨打印喷墨，形成柔性电路板的盖板。

公开(公告)号：US20070283848A1

公开(公告)日：2007-12-13

申请号：US11797631

申请日：2007-05-04

Applicant: Tae-Hoon Kim ,  Jae-Woo Joung ,  Sung-Nam Cho ,  Sung-Il Oh ,  Hye-Jin Cho

Inventor： Tae-Hoon Kim ,  Jae-Woo Joung ,  Sung-Nam Cho ,  Sung-Il Oh ,  Hye-Jin Cho

IPC: C09D11/02

CPC classification number: C09D11/322 ,  B22F1/0074 ,  B22F2998/00 ,  C09D11/36 ,  B22F1/0018

Abstract: The present invention relates to a metal ink composition for inkjet printing, more particularly to a metal ink composition which includes 20 to 85 weight % of metal nanoparticles and 15 to 80 weight % of organic solvent, where the organic solvent is made of an ethylene glycol-based ether or a mixed solvent including an ethylene glycol-based ether. The invention provides a metal ink composition in which an organic solvent suited for an inkjet head is used to improve the ejection, storage, and viscosity properties of the ink.

Abstract translation: 本发明涉及一种用于喷墨印刷的金属油墨组合物，更具体地涉及一种金属油墨组合物，其包含20至85重量％的金属纳米颗粒和15至80重量％的有机溶剂，其中有机溶剂由乙二醇 的醚或包含乙二醇基醚的混合溶剂。 本发明提供了一种金属油墨组合物，其中使用适用于喷墨头的有机溶剂来改善油墨的喷射，储存和粘度特性。

公开(公告)号：US20070190725A1

公开(公告)日：2007-08-16

申请号：US11740525

申请日：2007-04-26

Applicant: Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

Inventor： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

Abstract translation: 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

公开(公告)号：US20070056402A1

公开(公告)日：2007-03-15

申请号：US11520731

申请日：2006-09-14

Applicant: Sung-Nam Cho ,  Sung-II Oh ,  Hye-Jin Cho

Inventor： Sung-Nam Cho ,  Sung-II Oh ,  Hye-Jin Cho

IPC: B22F9/24

CPC classification number: B22F1/0018 ,  B22F1/0014 ,  B22F9/24 ,  B82Y30/00 ,  C09D11/30

Abstract: The present invention provides a method of producing metal nanoparticles, having a high yield rate and uniform size achieved by employing a heterologous reducing agent that considerably reduces unreactant, and using ethylene glycol that allows effective separation of desired metal nanoparticles. In addition, the present invention provides metal nanoparticles having high dispersion stability achieved by capping with polyvinyl pyrrolidone(PVP) and conductive ink including these metal nanoparticles. One aspect of the invention may provide a method of producing nanoparticles comprising, (a) mixing ethylene glycol, capping molecules and a reducing agent, (b) mixing a metal precursor with alcohol-based compound and reacting it with the mixture of (a), and (c) finishing the reaction by adding acetone and ethylene glycol to the reaction solution (b).

Abstract translation: 本发明提供一种生产金属纳米粒子的方法，其具有高的产率和均匀的尺寸，其通过使用显着减少未反应物的异源还原剂和使用允许有效分离所需金属纳米粒子的乙二醇来实现。 此外，本发明提供了通过用聚乙烯吡咯烷酮（PVP）和包含这些金属纳米颗粒的导电油墨进行封端而实现的具有高分散稳定性的金属纳米颗粒。 本发明的一个方面可以提供一种生产纳米颗粒的方法，其包括（a）混合乙二醇，封端分子和还原剂，（b）将金属前体与醇基化合物混合并使其与（a） ，和（c）通过向反应溶液（b）中加入丙酮和乙二醇来完成反应。

公开(公告)号：US20060289907A1

公开(公告)日：2006-12-28

申请号：US11513474

申请日：2006-08-31

Applicant: Sung-Min Kim ,  Dong-Gun Park ,  Sung-Young Lee ,  Hye-Jin Cho ,  Eun-Jung Yun ,  Shin-Ae Lee ,  Chang-Woo Oh ,  Jeong-Dong Choe

Inventor： Sung-Min Kim ,  Dong-Gun Park ,  Sung-Young Lee ,  Hye-Jin Cho ,  Eun-Jung Yun ,  Shin-Ae Lee ,  Chang-Woo Oh ,  Jeong-Dong Choe

IPC: H01L29/76 ,  H01L21/8234

CPC classification number: H01L29/66651 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/0653

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract translation: 在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

公开(公告)号：US20060208230A1

公开(公告)日：2006-09-21

申请号：US11371101

申请日：2006-03-09

Applicant: Hye-Jin Cho ,  Byung-Ho Jun

Inventor： Hye-Jin Cho ,  Byung-Ho Jun

IPC: H01B1/12

CPC classification number: H05K1/097 ,  C09D11/30 ,  H01B1/02 ,  H01B1/16 ,  H05K3/125

Abstract: The PCB manufactured by spraying conductive ink dispersed with Ag—Pd alloy nanoparticles and curing to form wiring according to the present invention provides reduced migration of Ag ions. Further, the present invention provides a method for manufacturing PCB which exhibits competitive price, and excellent conductivity and anti-migration. As one aspect of the present invention, a conductive ink comprising Ag—Pd alloy nanoparticles, wherein the Ag—Pd alloy nanoparticles includes Pd in the range of from 5 weight % to 40 weight %.

Abstract translation: 通过喷涂分散有Ag-Pd合金纳米颗粒并固化以形成根据本发明的布线的PCB制造的PCB减少了Ag离子的迁移。 此外，本发明提供了具有竞争力的价格，优异的导电性和抗迁移性的PCB制造方法。 作为本发明的一个方面，包含Ag-Pd合金纳米颗粒的导电油墨，其中Ag-Pd合金纳米颗粒包括在5重量％至40重量％范围内的Pd。