摘要:
A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要:
A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要:
Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.
摘要:
A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要:
The present invention discloses an address buffer and a semiconductor memory device having the address buffer. The address buffer comprises a first buffer for latching a signal in response to a first control signal in a normal operation mode in the semiconductor memory device and generating a buffered signal by buffering the latched signal in response to a second control signal, and a second buffer for maintaining a mode-setting signal in a reset status in the normal operation mode and for outputting the mode-setting signal by using the latched signal in response to the first control signal and a mode-setting command in a mode-setting operation mode. Accordingly, the mode-setting signal is generated only in the mode-setting operation mode, thereby reducing undesirable current consumption.
摘要:
Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.
摘要:
A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level, powering-up the internal power voltage in relation to the external power voltage during the first period, and continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.
摘要:
A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要:
A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要:
A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to the shared memory region and the ports. The data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.