摘要:
A hybrid charge pump including a hybrid circuit configured to snub an over shoot or under shoot present in an input pulse in a snubbing operation if a level of the pulse is a first level, store the pulse in a charging operation if the level of the pulse is a second level different from the first level, and generate a negative voltage from the stored pulse in a negative voltage generation operation.
摘要:
In a clock-based soft-start circuit configured to generate a soft-start reference voltage that restrains an inrush current at an initialization of power supplied to a DC-DC converter, the clock-based soft-start circuit comprises a time setting unit configured to set a soft-start time period in response to a clock signal. A ramp circuit is configured to generate a soft-start reference voltage which is ramped upward or downward between a base level and a reference voltage level during the soft start time period set by the time setting unit. In this manner, the clock-based soft-start circuit is applicable for all DC-DC converters and the soft-start in a linear slope is possible.
摘要:
A hybrid charge pump including a hybrid circuit configured to snub an over shoot or under shoot present in an input pulse in a snubbing operation if a level of the pulse is a first level, store the pulse in a charging operation if the level of the pulse is a second level different from the first level, and generate a negative voltage from the stored pulse in a negative voltage generation operation.
摘要:
A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples.
摘要:
A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples.
摘要:
A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples.
摘要:
A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples.
摘要:
Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.
摘要:
A power converter includes a zero-current detector having an adjustable offset voltage. The power converter includes a power converting unit and a switch driving circuit. The power converting unit generates a DC output voltage based on a pull-up driving signal, a pull-down driving signal and a DC input voltage. The switch driving circuit generates a first detection voltage signal based on the DC output voltage. The switch driving circuit includes a zero-current detector configured to adjust an offset voltage based on the first detection voltage signal and generate a zero-current detecting signal based on the offset voltage. The offset voltage and the zero-current detecting signal are associated with a current in the power converting unit. The switch driving circuit also includes a pulse-frequency modulating circuit configured to perform a pulse-frequency modulation (PFM) to generate the pull-up driving signal and the pull-down driving signal based on the zero-current detecting signal.
摘要:
A power converter includes a zero-current detector having an adjustable offset voltage. The power converter includes a power converting unit and a switch driving circuit. The power converting unit generates a DC output voltage based on a pull-up driving signal, a pull-down driving signal and a DC input voltage. The switch driving circuit generates a first detection voltage signal based on the DC output voltage. The switch driving circuit includes a zero-current detector configured to adjust an offset voltage based on the first detection voltage signal and generate a zero-current detecting signal based on the offset voltage. The offset voltage and the zero-current detecting signal are associated with a current in the power converting unit. The switch driving circuit also includes a pulse-frequency modulating circuit configured to perform a pulse-frequency modulation (PFM) to generate the pull-up driving signal and the pull-down driving signal based on the zero-current detecting signal