利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

49 条记录 (耗时 0.021 秒)

    Magnetic tunnel junction structures and methods of fabrication
    2.
    发明授权
    Magnetic tunnel junction structures and methods of fabrication 有权
    磁隧道结结构和制造方法

    公开(公告)号：US07504266B2

    公开(公告)日：2009-03-17

    申请号：US11141057

    申请日：2005-06-01

    申请人： Kyu-Mann Lee ,  Hyun-Jo Kim ,  Jeong-Hee Park ,  Tae-Wan Kim ,  I-Hun Song ,  Seok-Jae Chung

    发明人： Kyu-Mann Lee ,  Hyun-Jo Kim ,  Jeong-Hee Park ,  Tae-Wan Kim ,  I-Hun Song ,  Seok-Jae Chung

    IPC分类号： H01L21/00

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08

    摘要： A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.

    摘要翻译： 一种适用于具有包括铂，钌，铱，铑，锇，钯或其氧化物层的底部电极的MRAM器件的MTJ结构的方法，并且具有降低的表面粗糙度以改善所得到的磁滞回线特性 MTJ结构。 底部电极层也可以组合常规双层结构的接合层和底部电极的功能，从而简化了制造过程。

    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS
    3.
    发明申请
    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS 失效
    包括选择的参考存储器单元的电阻存储器件

    公开(公告)号：US20090067216A1

    公开(公告)日：2009-03-12

    申请号：US12265941

    申请日：2008-11-06

    申请人： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    发明人： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC分类号： G11C11/00 ,  G11C11/02 ,  G11C7/00

    CPC分类号： G11C11/1675 ,  G11C11/1673

    摘要： A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.

    摘要翻译： 磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流 源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流 耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线 与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为将第二偏置电压施加到未被选择以在读取期间访问的第一或第二存储器单元 操作。

    Resistive memory devices including selected reference memory cells and methods of operating the same
    5.
    发明申请
    Resistive memory devices including selected reference memory cells and methods of operating the same 审中-公开
    电阻式存储器件包括所选择的参考存储单元及其操作方法

    公开(公告)号：US20070103964A1

    公开(公告)日：2007-05-10

    申请号：US11580766

    申请日：2006-10-13

    申请人： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    发明人： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1673

    摘要： A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be conducted via a pair of opposing current source transistors located on first and second opposing sides of the first block to provide the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to provide the programming current parallel to the second block.

    摘要翻译： 访问电阻式存储器件的方法可以包括在耦合到第二字线的第二电阻存储器单元块的读取操作期间将预定电压电平施加到耦合到第一电阻存储器单元块的第一字线。编程电流可以 位于第一块的第一和第二相对侧上的一对相对的电流源晶体管导通，以提供编程电流，从而从第一端到第二端跨越与第一块中的电阻式存储单元耦合的位线，并提供 编程电流平行于第二块。

    Magnetic random access memory device and method of forming the same
    6.
    发明申请
    Magnetic random access memory device and method of forming the same 有权
    磁性随机存取存储器件及其形成方法

    公开(公告)号：US20060174473A1

    公开(公告)日：2006-08-10

    申请号：US11347280

    申请日：2006-02-06

    申请人： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    发明人： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    IPC分类号： G11B5/33 ,  G11B5/127 ,  H04R31/00

    CPC分类号： G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

    摘要： Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

    摘要翻译： 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

    ELECTROSTATIC DISCHARGE PROTECTION DEVICES
    9.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICES 审中-公开
    静电放电保护装置

    公开(公告)号：US20160211254A1

    公开(公告)日：2016-07-21

    申请号：US14599593

    申请日：2015-01-19

    申请人： DAE-LIM KANG ,  HYUN-JO KIM ,  JONG-MIL YOUN ,  SOO-HUN HONG

    发明人： DAE-LIM KANG ,  HYUN-JO KIM ,  JONG-MIL YOUN ,  SOO-HUN HONG

    IPC分类号： H01L27/02 ,  H01L29/16 ,  H01L27/088

    CPC分类号： H01L27/0266 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1608

    摘要： An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

    摘要翻译： ESD保护装置包括具有沿第一方向延伸的有源鳍片的衬底，多个栅极结构，其以相对于第一方向以给定角度在第二方向延伸并且部分覆盖有源鳍片，凹槽中的外延层 在栅极结构之间的有源鳍片的一部分上，在外延层下方的杂质区域和与外延层接触的接触插塞。 在第一方向上，杂质区域的中心部分比杂质区域的边缘部分厚。 接触插塞位于杂质区域的中心部分之上。

    Magnetic Memory Device
    10.
    发明申请
    Magnetic Memory Device 有权
    磁存储器件

    公开(公告)号：US20100213558A1

    公开(公告)日：2010-08-26

    申请号：US12773451

    申请日：2010-05-04

    申请人： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

    发明人： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

    IPC分类号： H01L29/82

    CPC分类号： G11C11/15 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3281 ,  H01F41/302 ,  H01L43/08

    摘要： A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

    摘要翻译： 提供磁存储器件。 磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。 在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。 在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。 在存储和无引导模式之间插入一个自由的反转模式。 自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。