公开(公告)号：US08456012B2

公开(公告)日：2013-06-04

申请号：US12568086

申请日：2009-09-28

Applicant: Chang-Woo Shin ,  Hyun-Soo Chung ,  Eun-Chul Ahn ,  Jum-Gon Kim ,  Jin-Ho Chun

Inventor： Chang-Woo Shin ,  Hyun-Soo Chung ,  Eun-Chul Ahn ,  Jum-Gon Kim ,  Jin-Ho Chun

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76841 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/12044

Abstract: A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.

Abstract translation: 提供一种包括铜焊盘，焊盘阻挡层和金属再分布层的互连结构的半导体器件，其互连结构及其制造方法。 半导体器件包括设置在第一层上的铜焊盘，包括设置在铜焊盘上的钛的焊盘阻挡层，设置在焊盘阻挡层上的无机绝缘层，设置在无机绝缘层上的缓冲层，其中无机绝缘 所述缓冲层暴露所述焊盘阻挡层的一部分，设置在所述暴露的缓冲层上的种子金属层，设置在所述种子金属层上的金属再分配层以及设置在所述金属再分配层上的第一保护层。

公开(公告)号：US20120299194A1

公开(公告)日：2012-11-29

申请号：US13569653

申请日：2012-08-08

Applicant: Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

Inventor： Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Abstract translation: 半导体器件包括半导体衬底和通孔电极。 通孔电极在基板上具有第一部分并且朝向基板延伸并且具有从第一部分延伸到基板中的多个尖峰，每个尖峰彼此间隔开。

公开(公告)号：US08232644B2

公开(公告)日：2012-07-31

申请号：US13346191

申请日：2012-01-09

Applicant: Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract translation: 在具有应力消除间隔物的半导体器件封装及其制造方法中，从芯片本体延伸的金属互连指状物提供芯片互连。 金属手指通过应力消除间隔物与芯片的主体隔离。 在一个示例中，这种隔离采取气隙的形式。 在另一个实例中，这种隔离采用弹性体材料的形式。 在这两种情况下，都避免了金属互连指和芯体之间的热膨胀系数的不匹配，从而减轻了与开裂和分层相关的问题，从而提高了器件的产量和器件的可靠性。

公开(公告)号：US08143693B2

公开(公告)日：2012-03-27

申请号：US12098352

申请日：2008-04-04

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Hyun-Soo Chung

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Hyun-Soo Chung

IPC: H01L29/00

CPC classification number: H01L23/525 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L2224/02233 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00

Abstract: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案， 第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。 还提供了一种制造该方法的方法。

公开(公告)号：US08110922B2

公开(公告)日：2012-02-07

申请号：US12588231

申请日：2009-10-08

Applicant: Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

Abstract translation: 晶片级半导体模块可以包括安装在模块板上的模块板和IC芯片组。 IC芯片组可以包括在相邻IC芯片之间具有划线区域的多个IC芯片。 每个IC芯片可以具有具有多个芯片焊盘和后表面的有源表面的半导体衬底。 可以在每个IC芯片的半导体衬底的有源表面上提供钝化层，并且可以具有可以暴露芯片焊盘的开口。 密封部分可以形成在划线区域中。

公开(公告)号：US07851256B2

公开(公告)日：2010-12-14

申请号：US12285923

申请日：2008-10-16

Applicant: Hyun-soo Chung ,  Dong-ho Lee ,  Seong-deok Hwang ,  Sun-won Kang ,  Seung-duk Baek

Inventor： Hyun-soo Chung ,  Dong-ho Lee ,  Seong-deok Hwang ,  Sun-won Kang ,  Seung-duk Baek

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16112 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/81805 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014

Abstract: Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.

Abstract translation: 提供了一种制造片上芯片（COC）半导体器件的方法。 片上芯片（COC）半导体器件的制造方法可以包括：准备具有在其中形成有至少一个不连续点的金属布线的第一半导体器件，制备第二半导体器件，其中至少一个凸点形成在 所述第二半导体器件对应于所述至少一个不连续点，将所述第一半导体器件对准到所述第二半导体器件上，并且将所述第二半导体器件的所述至少一个突起连接到形成在所述第二半导体器件的所述金属布线中的所述至少一个不连续点 第一半导体器件。

公开(公告)号：US07847416B2

公开(公告)日：2010-12-07

申请号：US12498913

申请日：2009-07-07

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US07830017B2

公开(公告)日：2010-11-09

申请号：US11950251

申请日：2007-12-04

Applicant: In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

Inventor： In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Abstract translation: 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

公开(公告)号：US07777345B2

公开(公告)日：2010-08-17

申请号：US12132925

申请日：2008-06-04

Applicant: Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05561 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014

Abstract: A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.

Abstract translation: 公开了一种具有通孔的半导体器件及其制造方法。 在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。 具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。 第二绝缘层形成在布线层的上部和第一孔中。 具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。 通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。 在通孔中形成贯通电极。

公开(公告)号：US07740145B2

公开(公告)日：2010-06-22

申请号：US10540566

申请日：2003-12-23

Applicant: Hyun-Soo Chung

Inventor： Hyun-Soo Chung

IPC: B65D39/12

CPC classification number: B65D49/04 ,  B65D49/00 ,  B65D55/12

Abstract: A bottle cap is disclosed, which displays an opened state and cannot contain contents again once it is opened. The bottle cap includes a cap having a screw formed on its inner surface to be engaged with a screw formed on an outer surface of a nozzle of a bottle, a reverse moving means connected to the cap and ascending in a direction opposite to a descending direction of the cap as the cap is rotated downwardly, a rod shaped nut having a screw engaged with the reverse moving means and moving up and down in a screw direction without rotation, and a display installed in the lower portion of the nut, displaying an opened state of the cap by hanging a part of the cap in the nozzle as the cap is moved downwardly by being pushed by the nut if the cap is opened.

Abstract translation: 公开了一种瓶盖，其显示打开的状态，并且一旦打开状态就不能再含有内容物。 瓶盖包括盖，该盖具有形成在其内表面上的螺钉，以与形成在瓶的喷嘴的外表面上的螺钉相接合;反向移动装置，连接到盖并沿与下降方向相反的方向上升 盖帽旋转向下旋转的杆状螺母，具有与反向移动装置接合的螺钉并沿螺钉方向上下移动而不旋转的杆形螺母，以及安装在螺母下部的显示器， 如果盖子被打开，当盖子通过被螺母推动而向下移动时，将盖子的一部分悬挂在喷嘴中。