公开(公告)号：US20110001467A1

公开(公告)日：2011-01-06

申请号：US12791241

申请日：2010-06-01

申请人： Hyung Chan CHOI ,  Hee Joo CHOI ,  Seung Man SHIN ,  Hui-Chung BYUN

发明人： Hyung Chan CHOI ,  Hee Joo CHOI ,  Seung Man SHIN ,  Hui-Chung BYUN

IPC分类号： G01R19/00

CPC分类号： G01R31/3004 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A method of optimizing a driving voltage of an electronic device includes; iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails, and then selecting as an operating level for the driving voltage, a level of the driving voltage for an iteration just prior to an iteration in which the operation fails.

摘要翻译： 优化电子设备的驱动电压的方法包括： 迭代地改变提供给电子设备的驱动电压的电平，并且每次迭代执行电子设备的操作，直到操作失败，然后选择驱动电压的操作电平，用于迭代的驱动电压的电平 就在操作失败的迭代之前。

公开(公告)号：US20120191964A1

公开(公告)日：2012-07-26

申请号：US13314666

申请日：2011-12-08

申请人： JONG-MIN LEE ,  Hyung-Chan Choi ,  Hee-Joo Choi ,  Seung-Man Shin

发明人： JONG-MIN LEE ,  Hyung-Chan Choi ,  Hee-Joo Choi ,  Seung-Man Shin

IPC分类号： G06F9/00 ,  G06F12/00

CPC分类号： G06F11/2284 ,  G06F9/4401 ,  G06F11/2289

摘要： A method of booting an information handling system including a volatile memory device to be selectively tested during a booting operation, the method comprising a step of reading current system configuration information from the information handling system, a step of comparing the current system configuration information with corresponding prestored system configuration information in a nonvolatile memory device, and a step of selectively performing a test for the volatile memory device according to a result of the comparison.

摘要翻译： 一种引导包括易失性存储器件的信息处理系统的方法，在引导操作期间被选择性地测试，所述方法包括从信息处理系统读取当前系统配置信息的步骤，将当前系统配置信息与相应的 非易失性存储装置中的预先存储的系统配置信息，以及根据比较结果选择性地对易失性存储装置进行测试的步骤。

公开(公告)号：US20050281114A1

公开(公告)日：2005-12-22

申请号：US10951053

申请日：2004-09-27

申请人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

发明人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

IPC分类号： G11C7/02 ,  G11C5/00 ,  G11C5/14 ,  G11C11/407

CPC分类号： G11C5/147 ,  G11C5/14

摘要： Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

摘要翻译： 至少一个共享电容器的去耦电容分布在多个电压源之间，以便在半导体器件的面积最小的情况下提高性能。 这些电压源的高节点和低节点各自包括至少两个不同的节点，用于在电压源处降低噪声。 本发明应用于根据半导体器件的位组织将可变数量的共用电容器耦合到数据充电电压源的特别优点。

公开(公告)号：US20050078545A1

公开(公告)日：2005-04-14

申请号：US10941446

申请日：2004-09-15

申请人： Moo-sung Chae ,  Hyung-chan Choi

发明人： Moo-sung Chae ,  Hyung-chan Choi

IPC分类号： G11C11/40 ,  G11C8/00 ,  G11C11/408 ,  G11C29/46

CPC分类号： G11C7/1066 ,  G11C11/401 ,  G11C11/4087 ,  G11C29/46 ,  G11C2029/1204

摘要： There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal. A column selection line signal can be generated without an increase in circuit logic, depending on a type of operation mode. Accordingly, it is possible to effectively realize CCD=1tCK in a semiconductor memory device, which operates in the DDR2 mode, in a test operation mode.

摘要翻译： 提供了用于控制列选择线信号的生成的方法和电路。 该方法包括确定当前模式是正常操作模式还是测试操作模式; 当当前模式是测试操作模式时，接收激活的测试操作模式信号和激活的第一时钟信号，并输出具有与第一时钟信号的激活时间成比例的激活时间的列选择线信号; 并且当当前模式是正常操作模式时，响应于所激活的第一时钟信号输出被激活的列选择线信号，并响应于激活的第二时钟信号被停用。 第一时钟信号的激活时间与外部时钟信号的激活时间成比例。 在测试操作模式下，在外部时钟信号的一个周期内执行命令。 根据操作模式的类型，可以产生列选择线信号而不增加电路逻辑。 因此，可以在测试操作模式中在以DDR2模式工作的半导体存储器件中有效地实现CCD = 1tCK。

公开(公告)号：US07352646B2

公开(公告)日：2008-04-01

申请号：US11024348

申请日：2004-12-27

申请人： Hyung-Chan Choi ,  Chi-Wook Kim

发明人： Hyung-Chan Choi ,  Chi-Wook Kim

IPC分类号： G11C8/00

CPC分类号： G11C5/14

摘要： A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.

摘要翻译： 一种半导体存储器件，其通过有效地定位去耦电容器来降低施加到读出放大器的第一和第二电源电压的电平变化，从而提高了操作性能。 去耦电容器布置在多个第一和第二读出放大器的空白区域上并且连接在第一和第二电源电压线之间。 多个全局数据I / O线对垂直于多个本地数据I / O线对的方向排列。

公开(公告)号：US07110316B2

公开(公告)日：2006-09-19

申请号：US10951053

申请日：2004-09-27

申请人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

发明人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/14

摘要： Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

摘要翻译： 至少一个共享电容器的去耦电容分布在多个电压源之间，以便在半导体器件的面积最小的情况下提高性能。 这些电压源的高节点和低节点各自包括至少两个不同的节点，用于在电压源处降低噪声。 本发明应用于根据半导体器件的位组织将可变数量的共享电容器耦合到数据充电电压源的特别优点。

公开(公告)号：US06992949B2

公开(公告)日：2006-01-31

申请号：US10941446

申请日：2004-09-15

申请人： Moo-sung Chae ,  Hyung-chan Choi

发明人： Moo-sung Chae ,  Hyung-chan Choi

IPC分类号： G11C8/00

CPC分类号： G11C7/1066 ,  G11C11/401 ,  G11C11/4087 ,  G11C29/46 ,  G11C2029/1204

摘要： There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal. A column selection line signal can be generated without an increase in circuit logic, depending on a type of operation mode. Accordingly, it is possible to effectively realize CCD=1tCK in a semiconductor memory device, which operates in the DDR2 mode, in a test operation mode.

摘要翻译： 提供了用于控制列选择线信号的生成的方法和电路。 该方法包括确定当前模式是正常操作模式还是测试操作模式; 当当前模式是测试操作模式时，接收激活的测试操作模式信号和激活的第一时钟信号，并输出具有与第一时钟信号的激活时间成比例的激活时间的列选择线信号; 并且当当前模式是正常操作模式时，响应于所激活的第一时钟信号输出被激活的列选择线信号，并响应于激活的第二时钟信号被停用。 第一时钟信号的激活时间与外部时钟信号的激活时间成比例。 在测试操作模式下，在外部时钟信号的一个周期内执行命令。 根据操作模式的类型，可以产生列选择线信号而不增加电路逻辑。 因此，可以在测试操作模式中在以DDR2模式工作的半导体存储器件中有效地实现CCD = 1tCK。

公开(公告)号：US20050152203A1

公开(公告)日：2005-07-14

申请号：US11024348

申请日：2004-12-27

申请人： Hyung-Chan Choi ,  Chi-Wook Kim

发明人： Hyung-Chan Choi ,  Chi-Wook Kim

IPC分类号： G11C7/08 ,  G11C5/02 ,  G11C5/14

CPC分类号： G11C5/14

摘要： A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.

摘要翻译： 一种半导体存储器件，其通过有效地定位去耦电容器来降低施加到读出放大器的第一和第二电源电压的电平变化，从而提高了操作性能。 去耦电容器布置在多个第一和第二读出放大器的空白区域上并且连接在第一和第二电源电压线之间。 多个全局数据I / O线对垂直于多个本地数据I / O线对的方向排列。