摘要:
In one exemplary embodiment, an object region tracking and picturing module is constructed on a moving platform of a mobile end and a remote control module is constructed on anther platform for an image object region tracking system. The two modules communicate with each other via a digital network for delivering required information. The object region tracking and picturing module uses a real-time image backward search technology to store at least an image frame previously captured on the moving platform into a frame buffer, and start tracking an object region from the position pointed out by the remote control module to a newest image frame captured on the moving platform, then find out a relative position on the newest image frame for the tracked object region.
摘要:
A handoff method in a wireless local area network (WLAN) and an apparatus using the same are provided. A mobile station (MS) switches between a data transceiving mode and a probing mode at a predefined interval when the MS is transmitting/receiving packages. In the probing mode, the MS probes one or more channels each time and selects an access point (AP) for handoff from the probing result according to a predetermined rule, so as to re-establish a network connection.
摘要:
A transflective liquid crystal display (LCD) includes at least a transmission pixel region and at least a reflection pixel region positioned in a pixel region. The transmission region includes at least a transmissive electrode connected to a first switching element. The reflection pixel region includes at least a reflective electrode connected to a second switching element. The transmissive and the reflective electrodes are controlled respectively by independent switching elements.
摘要:
A thin film transistor for use in an active matrix liquid crystal display includes a substrate, a source and a drain regions, and at least a gate electrode. The substrate includes therein a plurality of intrinsic regions, at least one first doped region and two second doped regions. The first doped region is disposed between the plurality of intrinsic regions. The plurality of intrinsic regions are linked together to form a connection structure via the first doped region, and the two second doped regions are disposed at both ends of the connection structure, respectively. The source and the drain regions are coupled to the two second doped regions disposed at both ends of the connection structure, respectively. The gate electrode is disposed over the plurality of intrinsic regions, such that the periphery of each of the plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.
摘要:
Cell circuitry in an array on a substrate includes a TFT or other structure with a series of two or more channels and with an intrachannel region between each pair of adjacent channels in the series. Each intrachannel region has a continuously distribution of dopant particles and the distribution of dopant particles in the intrachannel regions together controls reverse gate bias leakage current without significantly reducing ON current. The average dopant density in intrachannel regions can be sufficiently low to ensure that reverse gate bias leakage current is approximately constant across a range of reverse gate bias voltages. For applications such as light valve arrays, sensor arrays, and memory arrays in which each cell includes a capacitive element for storing a level of charge in one of two or more voltage bands, the average dopant density of intrachannel regions can ensure that reverse gate bias leakage current is sufficiently low that a level of charge stored by the capacitive element remains within its voltage band during a storage period.
摘要:
This disclosure relates to semiconductor varactors, such as thin film poly-Si varactors, which have larger effective gate areas in accumulation than in depletion, together with capacitive switching ratios which are essentially determined by the ratio of their effective gate area in accumulation to their effective gate area in depletion. To that end, such a varactor has a fully depletable active semiconductor layer, such as a thin poly-Si film, and is constructed so that at least a part of its active layer is sandwiched between a relatively thin dielectric layer and a relatively thick dielectric layer. The thin dielectric layer, in turn, is sandwiched between the active semiconductor layer and a gate electrode. Furthermore, one or more ground electrodes are electrically coupled to laterally offset portions of the active semiconductor layer in partial overlapping alignment with the gate electrode. In keeping with this invention, the capacitance per unit surface area of the thin dielectric layer is so much greater than the capacitance per unit surface area of the thick dielectric layer that the series capacitance of the depleted active semiconductor layer and the thick dielectric layer negligibly contribute to the capacitance of the varactor when it is operating in its depletion mode. Top-gate and bottom-gate embodiments having ground electrodes which are coplanar with the active semiconductor layer, ground electrodes which are in a plane adjacent to the active semiconductor layer, segmented gate electrodes and segmented ground electrodes, and continuous gate electrodes and segmented ground electrodes are disclosed.
摘要:
A thin film SOI CMOS device wheren the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.
摘要:
A design approach for a panel including a luminiferous unit and a driving unit. The luminiferous unit comprises first and second color components respectively constituting first and second light component sources. First and second light components are emitted from the first and the second light component sources. The color of the first light component differs from that of the second light component. The design approach comprises defining a specific relationship according to a characteristic between the first and the second color components; and designing the driving unit according to the specific relationship.
摘要:
A transflective liquid crystal display (LCD) includes at least a transmission pixel region and at least a reflection pixel region positioned in a pixel region. The transmission region includes at least a transmissive electrode connected to a first switching element. The reflection pixel region includes at least a reflective electrode connected to a second switching element. The transmissive and the reflective electrodes are controlled respectively by independent switching elements.
摘要:
A six mask-steps method for fabricating liquid crystal display is described. A driving area and a pixel area are defined by a first mask step. Gates on the driving/pixel area and upper electrodes of capacitors on the pixel area are defined by a second mask step. Then, using the gates and the upper electrodes as a mask, a source/drain, channel region and lower electrode are formed in the driving/pixel area by an ion-doping process. A second insulation layer is formed and covers the insulation substrate. A plurality of first openings is formed by the third mask step and the gate and the source/drain are exposed. A second conductive layer is formed and covers the second insulation layer and the first opening is filled. Then, the second conductive layer is patterned, and a source/drain line is formed and contacts electrically with the source/drain by the fourth mask step. A dielectric layer is formed and covers the second insulation layer and the second conductive layer; the dielectric layer has a planar surface. A second opening is formed by the fifth mask step and the drain line on the pixel area is exposed. Finally, a pixel electrode is defined by the sixth mask step and contacts electrically with the drain line.