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1.发明申请SERIALIZER/DESERIALIZER CIRCUIT FOR JITTER SENSITIVITY CHARACTERIZATION 有权串行器/ DESERIALIZER电路，用于智能感应特性公开(公告)号：US20040243899A1
公开(公告)日：2004-12-02
申请号：US10707961
申请日：2004-01-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Dominique P. Bonneau , Philippe Hauviller , Vincent Vallet
IPC: G11B005/00 , G06K005/04 , G01R031/28 , G11B020/20
CPC classification number: G01R31/31709 , G01R31/31715 , G01R31/31725 , H03M9/00 , H04J2203/0062 , H04J2203/0089 , H04L1/205 , H04L1/243 , H04L1/244
Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data. Moreover, the perturbed data stream can be transmitted to any distant SERDES circuit (104) before it is looped back to the CDR circuit. By comparing the jitter sensitivity with and without using the transmission link (106), one can easily characterize the amount of jitter added by said link. A method of testing the jitter sensitivity of the CDR circuit is also disclosed.
Abstract translation: 本文公开了一种改进的串行器/解串器（SERDES）电路（102），其具有被配置为执行时钟和数据恢复（CDR）电路（108）的原位抖动灵敏度表征的内置自检能力。 为此，通常使用可变延迟（DEL）线（116），在串行器（120）输出端口向串行数据流添加延迟扰动。 然后，干扰的串行数据流被环回到CDR电路。 耦合到DEL线的控制逻辑（112）中的专用电路和解串行器电路（110）分析恢复的数据以表征CDR电路对抖动频率的灵敏度。 通过连续地修改所述串行数据流的输出延迟，即扰动的振幅和频率，可以产生非常接近实际抖动数据的干扰的串行数据流。 此外，扰动的数据流可以在被环回到CDR电路之前被发送到任何远端的SERDES电路（104）。 通过比较具有和不使用传输链路（106）的抖动灵敏度，可以容易地表征所述链路所添加的抖动量。 还公开了测试CDR电路的抖动灵敏度的方法。
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2.发明申请
公开(公告)号：US20250072297A1
公开(公告)日：2025-02-27
申请号：US18236380
申请日：2023-08-21
Applicant: International Business Machines Corporation
Inventor： Russell A. Budd , Jason S. Orcutt , Eric Zhang , Yves Martin
Abstract: An apparatus comprises optical apparatus, and electrical characterization apparatus. The optical apparatus and the electrical characterization apparatus comprise an integrated configuration to perform laser annealing operations for tuning junction resistances of superconducting tunnel junction devices on a quantum chip, and to perform in-situ resistance measurements to measure the junction resistances of the superconducting tunnel junction devices on the quantum chip.
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公开(公告)号：US20250072116A1
公开(公告)日：2025-02-27
申请号：US18452682
申请日：2023-08-21
Applicant: International Business Machines Corporation
Inventor： Juntao Li , Ruilong Xie , Julien Frougier , Min Gyu Sung , Chanro Park
IPC: H01L27/12 , H01L21/8234 , H01L21/84
Abstract: A semiconductor device comprises a first nanosheet transistor disposed on a semiconductor substrate, the first nanosheet transistor comprising a plurality of first gate structures, and a second nanosheet transistor disposed on the semiconductor substrate, the second nanosheet transistor comprising a plurality of second gate structures. Respective stacked spacer structures are disposed on respective sides of respective ones of the plurality of second gate structures, wherein each of the respective stacked spacer structures comprises a first spacer and a second spacer. Respective ones of the plurality of first gate structures comprise a first nanosheet gate portion and a gate dielectric layer around the first nanosheet gate portion. The respective ones of the plurality of second gate structures comprise a second nanosheet gate portion and at least two gate dielectric layers around the second nanosheet gate portion.
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公开(公告)号：US20250072113A1
公开(公告)日：2025-02-27
申请号：US18453285
申请日：2023-08-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ruilong Xie , James P. Mazza , Shahrukh Khan , Iqbal Rashid Saraf , Biswanath Senapati , Tenko Yamashita
IPC: H01L27/12
Abstract: A semiconductor device includes a first source/drain region, a first contact over the first source/drain region, a second source/drain region, and a lateral contact connecting the second source/drain region to a back end of line (BEOL). Portions of the first contact are recessed, and the lateral contact overlaps with the recessed portions of the first contact. The first source/drain region is formed over the second source/drain region.
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公开(公告)号：US20250071787A1
公开(公告)日：2025-02-27
申请号：US18383087
申请日：2023-10-24
Applicant: International Business Machines Corporation
Inventor： Maja Curic , Sagar Tayal
Abstract: The present disclosure relates to a method for prescheduling resources for user equipment in a wireless communication system. The method includes identifying a first network-based client-server application and a first user equipment, wherein the first user equipment includes a client side of the application. The method further includes determining a first usage profile for the first user equipment, wherein the first usage profile of the first user equipment indicates an activity pattern of the first user equipment for the first application. The method further includes using the first usage profile for predicting an upcoming activity of the first user equipment with regard to the first application. The method further includes using the upcoming activity for prescheduling resources for the first user equipment to enable the first user equipment to use the first application. The method further includes sending a notification to the first user equipment indicating the prescheduled resources.
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公开(公告)号：US20250071380A1
公开(公告)日：2025-02-27
申请号：US18238164
申请日：2023-08-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Connor Paul , Harry Hoots , Panav Setia , Jana H. Jenkins
IPC: H04N21/466 , H04N21/442
Abstract: Embodiments determine a user who is watching current content, receive content history of the user, calculate a consumption score (CS) based on series time, watch time, and consumption time of the content history, calculate a time to forget (TTF) threshold value based on the CS, the series time, and days since last viewed of the content history, compare the CS and the TTF threshold value to the current content watched by the user and current viewing habits of the user, and provide at least one suggestion to re-watch content of the content history based on the comparing.
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公开(公告)号：US20250070689A1
公开(公告)日：2025-02-27
申请号：US18238010
申请日：2023-08-25
Applicant: International Business Machines Corporation
Inventor： Sarbajit K. Rakshit , Jagabondhu Hazra , Manikandan Padmanaban
Abstract: An embodiment adjusts a position of a piezoelectric generator within a hollow cylindrical tube, the position adjusted to cause the tube to vibrate at a first resonant frequency in response to an acoustic stimulus, the piezoelectric generator configured to close one end of the tube, the tube further comprising an open end disposed at an opposite end of the tube from the piezoelectric generator. An embodiment adjusts, by applying a voltage to the piezoelectric generator, a resonant frequency of the piezoelectric generator, the adjusting changing the resonant frequency of the piezoelectric generator to the first resonant frequency.
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公开(公告)号：US20250068950A1
公开(公告)日：2025-02-27
申请号：US18236047
申请日：2023-08-21
Applicant: International Business Machines Corporation
Inventor： Eric Zhang , Jared Barney Hertzberg
IPC: G06N10/40
Abstract: Identify a plurality of candidate quantum computing chips to be arranged in a multi-chip quantum processor. Generate a current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor. Obtain results of tuning in accordance with the optimized tuning plan from at least one tuning system. Carry out tuning yield assessment based on results of the obtained tuning results. Repeat the steps of obtaining results and carrying out tuning yield assessment, based on tuning being incomplete and the current optimized tuning plan remaining viable.
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公开(公告)号：US20250068734A1
公开(公告)日：2025-02-27
申请号：US18453089
申请日：2023-08-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Roman Alexander Pletka , Dionysios Diamantopoulos , Slavisa Sarafijanovic , Charalampos Pozidis , Yves Alexandre Beraldo dos Santos , Andrew D. Walls
Abstract: Provided are a computer program product, system, and method for aggregating input/output operation features extracted from storage devices to form a machine learning vector to check for malware. Feature extraction functions are generated for the storage devices, indicating I/O operation features for the storage devices to gather. The feature extraction functions are communicated to the storage devices. The feature extraction functions transmitted to the storage devices cause the storage devices to gather information on I/O operation features, identified in the feature extraction functions, from the storage devices and transmit the information on the I/O operation features to the storage controller. The information on the I/O operation features are received from the storage devices. Information based on the received information on the I/O operation features are inputted into a machine learning model to output indication whether data in the storage devices contains malware.
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公开(公告)号：US20250068695A1
公开(公告)日：2025-02-27
申请号：US18455247
申请日：2023-08-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： ROBERT FREDERICK ENENKEL , CHRISTOPHER ANAND , SILVIA MELITTA MUELLER , LUCAS DUTTON , YU-SHIUAN WU
Abstract: Function approximation includes receiving a number value to be input to a function. The number value includes a first and second plurality of bits. A first approximation value of a function is determined using the first plurality of bits as an index to a first lookup table including a plurality of candidate first approximation values. A first correction coefficient is determined using the first plurality of bits as an index to a second lookup table including a plurality of candidate first correction coefficients. A second correction coefficient is determined by using the first plurality of bits as an index to a third lookup table including a plurality of candidate second correction coefficients. A second approximation value of the function is determined based on the first approximation value, the first correction coefficient, and the second plurality of bits.
