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14 条记录 (耗时 0.013 秒)

    Integrated Circuit and Method of Manufacturing an Integrated Circuit
    1.
    发明申请
    Integrated Circuit and Method of Manufacturing an Integrated Circuit 审中-公开
    集成电路和集成电路制造方法

    公开(公告)号：US20090267042A1

    公开(公告)日：2009-10-29

    申请号：US12109231

    申请日：2008-04-24

    申请人： Thomas D. Happ ,  Igor Kasko ,  Andreas Walter

    发明人： Thomas D. Happ ,  Igor Kasko ,  Andreas Walter

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72

    摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of resistance changing memory cells is provided. Each memory cell includes: a semiconductor substrate; a select device arranged within the semiconductor substrate; and a memory element being arranged above the semiconductor substrate. The select device is a diode comprising a first semiconductor area of a first conductive type and a second semiconductor area of a second conductive type which are arranged adjacent to each other such that a lateral pn-junction is formed. The first semiconductor area is connected to a word line arranged on or above the semiconductor substrate. The second semiconductor area is connected to the memory element via a conductive connection element.

    摘要翻译： 根据本发明的一个实施例，提供了包括多个电阻变化存储单元的集成电路。 每个存储单元包括：半导体衬底; 布置在所述半导体衬底内的选择器件; 以及设置在所述半导体衬底上方的存储元件。 选择装置是包括彼此相邻布置的第一导电类型的第一半导体区域和第二导电类型的第二半导体区域以形成侧向pn结的二极管。 第一半导体区域连接到布置在半导体衬底上或上方的字线​​。 第二半导体区域经由导电连接元件连接到存储元件。

    Spacer integration scheme in MRAM technology
    2.
    发明授权
    Spacer integration scheme in MRAM technology 有权
    MRAM技术中的间隔整合方案

    公开(公告)号：US06985384B2

    公开(公告)日：2006-01-10

    申请号：US10261709

    申请日：2002-10-01

    申请人： Gregory Costrini ,  John Hummel ,  Kia-Seng Low ,  Igor Kasko ,  Frank Findeis ,  Wolfgang Raberg

    发明人： Gregory Costrini ,  John Hummel ,  Kia-Seng Low ,  Igor Kasko ,  Frank Findeis ,  Wolfgang Raberg

    IPC分类号： G11C11/18

    CPC分类号： H01L43/12

    摘要： A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

    摘要翻译： 通过蚀刻由缓冲层，钉扎磁性层，隧道势垒层和自由磁性层组成的覆盖金属堆叠来制造磁阻存储器件。 通过形成覆盖自由层和隧道屏障界面侧面的保护性间隔物，消除了在蚀刻过程期间与溅射金属接合短路的问题。 在通过在阻挡层上停止的自由层的第一次蚀刻之后形成间隔物。 在间隔物形成之后，进行第二次蚀刻以隔离该装置。 器件隧道结的图案化使用一次性心轴方法制造，其能够在器件图案化工艺完成之后进行自对准接触。

    Method of producing a capacitor electrode with a barrier structure
    3.
    发明授权
    Method of producing a capacitor electrode with a barrier structure 有权
    制造具有阻挡结构的电容器电极的方法

    公开(公告)号：US06686265B2

    公开(公告)日：2004-02-03

    申请号：US10127618

    申请日：2002-04-22

    申请人： Gerhard Beitel ,  Annette Sänger ,  Igor Kasko

    发明人： Gerhard Beitel ,  Annette Sänger ,  Igor Kasko

    IPC分类号： H01L2144

    CPC分类号： H01L28/60 ,  H01L21/28568 ,  H01L21/31053 ,  H01L21/3212 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/75

    摘要： A capacitor electrode is produced with an underlying barrier structure. A barrier incorporation layer is used and a CMP (chemical mechanical polishing) process is employed in order to produce the barrier structure. The capacitor electrode with an underlying barrier structure is produced by depositing a barrier layer on a semiconductor substrate; forming a barrier structure from the barrier layer with a lithographic mask and an etching step; depositing a barrier incorporation layer covering the barrier structure and surrounding regions; and removing the barrier incorporation layer with chemical mechanical polishing until the barrier structure is uncovered, to thereby form the capacitor electrode above the barrier structure.

    摘要翻译： 制造具有下面的阻挡结构的电容器电极。 使用屏障结合层，并采用CMP（化学机械抛光）工艺以产生阻挡结构。 具有下面的阻挡结构的电容器电极通过在半导体衬底上沉积阻挡层来制造; 用光刻掩模和蚀刻步骤从阻挡层形成阻挡结构; 沉积覆盖阻挡结构和周围区域的势垒结合层; 并通过化学机械抛光去除阻挡层结合层，直到阻挡结构未被覆盖，从而在阻挡结构之上形成电容器电极。

    Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers
    4.
    发明授权
    Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers 有权
    具有磁性材料层的半导体器件的绝缘覆盖层和导电覆盖层

    公开(公告)号：US06680500B1

    公开(公告)日：2004-01-20

    申请号：US10210742

    申请日：2002-07-31

    申请人： Kia-Seng Low ,  John P. Hummel ,  Igor Kasko ,  Gregory Costrini

    发明人： Kia-Seng Low ,  John P. Hummel ,  Igor Kasko ,  Gregory Costrini

    IPC分类号： H01L2982

    CPC分类号： H01L27/222 ,  H01L21/76834 ,  H01L21/7684 ,  H01L43/08 ,  H01L43/12

    摘要： A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive lines (116) and exposed portions of the dielectric layer (112). The insulating cap layer (140) is patterned and etched to expose stack portions of the first conductive lines (116). A conductive cap layer (144) is deposited over the exposed portions of the first conductive lines (116). A magnetic material stack (118) is disposed over the insulating cap layer (140), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer (140) and conductive cap layer (144) protect the underlying first conductive line (116) material during the etching processes.

    摘要翻译： 一种半导体器件（100）及其制造方法，其中在衬底（110）上的电介质层（112）中形成多个第一导电线（116），并且绝缘覆盖层（140）设置在 第一导电线（116）和介电层（112）的暴露部分。 对绝缘覆盖层（140）进行图案化和蚀刻以暴露第一导电线（116）的堆叠部分。 导电盖层（144）沉积在第一导线（116）的暴露部分上。 磁性材料堆叠（118）设置在绝缘盖层（140）上，并且磁性材料堆叠被蚀刻以形成磁性堆叠。 在蚀刻过程期间，绝缘覆盖层（140）和导电覆盖层（144）保护下面的第一导电线（116）材料。

    Capacitor electrodes arrangement with oxygen iridium between silicon and oxygen barrier layer
    5.
    发明授权
    Capacitor electrodes arrangement with oxygen iridium between silicon and oxygen barrier layer 有权
    硅和氧阻隔层之间的电容器电极与氧铱排列

    公开(公告)号：US06573542B2

    公开(公告)日：2003-06-03

    申请号：US09891114

    申请日：2001-06-25

    申请人： Rainer Bruchhaus ,  Nicolas Nagel ,  Hermann Wendt ,  Igor Kasko ,  Robert Primig

    发明人： Rainer Bruchhaus ,  Nicolas Nagel ,  Hermann Wendt ,  Igor Kasko ,  Robert Primig

    IPC分类号： H01L2976

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55 ,  H01L28/60

    摘要： The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an oxygen barrier layer. The iridium layer is especially produced by a sputter process in an oxygen atmosphere with a low oxygen content. The oxygen-containing iridium layer is stale at temperatures up to 800° C. and withstands the formation of iridium silicide upon contact with the silicon-containing layer. Such micro-electronic structures are preferably used in semiconductor memories.

    摘要翻译： 本发明涉及一种微电子结构。 在该结构中，含氧铱层嵌入含硅层和氧阻隔层之间。 铱层特别是通过在低氧含量的氧气氛中的溅射工艺产生。 含氧铱层在高达800℃的温度下陈化，并在与含硅层接触时经受铱硅化物的形成。 这种微电子结构优选用于半导体存储器。

    Method of Manufacturing a Memory Cell, Memory Cell, Integrated Circuit, and Memory Module
    9.
    发明申请
    Method of Manufacturing a Memory Cell, Memory Cell, Integrated Circuit, and Memory Module 审中-公开
    存储单元，存储单元，集成电路和存储器模块的制造方法

    公开(公告)号：US20090073743A1

    公开(公告)日：2009-03-19

    申请号：US11856647

    申请日：2007-09-17

    申请人： Igor Kasko ,  Michael Kund

    发明人： Igor Kasko ,  Michael Kund

    IPC分类号： G11C11/24 ,  B05D5/12 ,  C21D9/00

    CPC分类号： H01L45/1658 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

    摘要： A method of fabricating a memory cell including a solid electrolyte layer doped with metallic material and an electrode layer arranged above the solid electrolyte layer. The method includes doping a solid electrolyte layer with metallic material and forming an electrode layer above the solid electrolyte layer, wherein doping the solid electrolyte layer is carried out before forming the electrode layer.

    摘要翻译： 一种制造包含掺杂有金属材料的固体电解质层和布置在固体电解质层上方的电极层的存储单元的方法。 该方法包括用金属材料掺杂固体电解质层并在固体电解质层上形成电极层，其中在形成电极层之前进行掺杂固体电解质层。

    Method for producing ferroelectric capacitors and integrated semiconductor memory chips
    10.
    发明授权
    Method for producing ferroelectric capacitors and integrated semiconductor memory chips 失效
    铁电电容器和集成半导体存储器芯片的制造方法

    公开(公告)号：US06875652B2

    公开(公告)日：2005-04-05

    申请号：US10638594

    申请日：2003-08-11

    申请人： Igor Kasko ,  Matthias Kroenke ,  Thomas Mikolajick

    发明人： Igor Kasko ,  Matthias Kroenke ,  Thomas Mikolajick

    IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8244

    CPC分类号： H01L21/7687 ,  H01L21/76888 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    摘要： The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual capacitor modules have an oxygen barrier between a lower capacitor electrode and an electrically conductive plug. At a site where it is not covered by the corresponding oxygen barrier, an unstructured adhesive layer is oxidized by the oxygen arising during the tempering process of the ferroelectric and forms insulating segments at the site in such a way that the lower capacitor electrodes of the ferroelectric capacitors are electrically insulated from one another. This makes it possible to dispense with structuring the adhesive layer. Furthermore, the layer serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

    摘要翻译： 本发明涉及一种用于制造铁电电容器的方法，所述铁电电容器使用堆叠原理构造并且用于集成半导体存储器芯片。 各个电容器模块在下部电容器电极和导电插塞之间具有氧气阻挡层。 在不被相应氧气阻挡层覆盖的位置处，非结构化粘合剂层被铁电体的回火过程中产生的氧氧化，并且在现场形成绝缘段，使得铁电体的下电容器电极 电容器彼此电绝缘。 这使得可以省略结构化粘合剂层。 此外，该层用作氧气的吸气剂并且抑制氧扩散到塞子。