公开(公告)号：US20100131678A1

公开(公告)日：2010-05-27

申请号：US12626857

申请日：2009-11-27

申请人： Hwang-Soo LEE ,  Jung-Keun Kim ,  Il-Song Han ,  Young Serk Shim

发明人： Hwang-Soo LEE ,  Jung-Keun Kim ,  Il-Song Han ,  Young Serk Shim

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： There is provided a direct memory access apparatus and a direct memory access method.The direct memory access apparatus of the present invention comprises: a variable transmission rule map unit for setting a transmission rule with a variable block length and a variable block interval as a unit of memory transmission rule; a direct memory access unit for sending data line of the variable block length and the variable block interval, in case of access to the unit of memory by using the unit of memory transmission rule determined by the variable transmission rule map unit; and an interface unit for retrieving the unit of memory transmission rule, which is necessary for sending the data line of the variable block length and the variable block interval, from the variable transmission rule map unit and sending the unit of memory transmission rule to the direct memory access unit.

摘要翻译： 提供了直接存储器访问装置和直接存储器访问方法。 本发明的直接存储器访问装置包括：可变传输规则映射单元，用于将具有可变块长度的传输规则和可变块间隔设置为存储器传输规则的单元; 在通过使用由可变传输规则映射单元确定的存储器发送规则的单元访问存储器单元的情况下，发送可变块长度和可变块间隔的数据线的直接存储器存取单元; 以及用于从可变传输规则映射单元检索用于发送可变块长度和可变块间隔的数据线所必需的存储器传输规则单元的接口单元，并将存储器传输规则单元发送到直接 存储器存取单元。

公开(公告)号：US5914868A

公开(公告)日：1999-06-22

申请号：US940004

申请日：1997-09-29

申请人： Il Song Han ,  Young Jae Choi ,  Dae Hwan Kim

发明人： Il Song Han ,  Young Jae Choi ,  Dae Hwan Kim

IPC分类号： G06G7/14 ,  G06F7/44 ,  G06G7/163 ,  G06G7/60 ,  G06N3/063 ,  H02M3/18 ,  G05F3/16 ,  G06F1/04

CPC分类号： G06G7/163 ,  G06N3/0635

摘要： A multiplier and a neural network synapse capable of removing nonlinear current using current mirror circuits. The multiplier produces a linear current by using MOS transistors operating in a nonsaturation region. The multiplier includes a first current mirror including a plurality of MOS transistors to form a first current and a second current mirror including a plurality of MOS transistors to form a second current, wherein the second current mirror is coupled in parallel to the first current mirror. As a result, the multiplier outputs an output current by subtracting a second current from said first current.

摘要翻译： 乘法器和神经网络突触能够使用电流镜像电路去除非线性电流。 乘法器通过使用在非饱和区域中工作的MOS晶体管产生线性电流。 乘法器包括：包括多个MOS晶体管以形成第一电流的第一电流镜和包括多个MOS晶体管以形成第二电流的第二电流镜，其中第二电流镜并联耦合到第一电流镜。 结果，乘法器通过从所述第一电流减去第二电流来输出输出电流。

公开(公告)号：US5889665A

公开(公告)日：1999-03-30

申请号：US940007

申请日：1997-09-29

申请人： Il Song Han

发明人： Il Song Han

IPC分类号： G06G7/14 ,  G06F7/44 ,  G06G7/164 ,  G06G7/60 ,  H02M3/18 ,  G05F3/16 ,  G06F1/04

CPC分类号： G06G7/164

摘要： A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q.sub.3 and a BJT Q.sub.5 and also the BJT Q.sub.3 is coupled in series to the n-channel MOSFET M1 between the voltage V.sub.1 and a ground voltage level. A second current mirror includes a BJT Q.sub.7 and a BJT Q.sub.8. A third current mirror includes a BJT Q.sub.4 and a BJT Q.sub.6. Consequently, input voltage signals V.sub.1 and V.sub.dc applied to the n-channel MOSFETs M1 determine the current I.sub.1 and input voltage signals V.sub.1 and V.sub.2 applied to the n-channel MOSFET M2 determine the current I.sub.2.

摘要翻译： 能够使用电流镜电路去除非线性电流的乘法器。 该乘法器通过BiCOMS工艺使用MOSFET和BJT器件。 该乘法器包括三个电流镜像电路。 第一电流镜包括BJT Q3和BJT Q5，并且BJT Q3与电压V1和接地电压电平之间的n沟道MOSFET M1串联耦合。 第二电流镜包括BJT Q7和BJT Q8。 第三电流镜包括BJT Q4和BJT Q6。 因此，施加到n沟道MOSFET M1的输入电压信号V1和Vdc确定电流I1，施加到n沟道MOSFET M2的输入电压信号V1和V2确定电流I2。

公开(公告)号：US08069280B2

公开(公告)日：2011-11-29

申请号：US12626857

申请日：2009-11-27

申请人： Hwang-Soo Lee ,  Jung-Keun Kim ,  Il-Song Han ,  Young Serk Shim

发明人： Hwang-Soo Lee ,  Jung-Keun Kim ,  Il-Song Han ,  Young Serk Shim

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： There is provided a direct memory access apparatus and a direct memory access method.The direct memory access apparatus of the present invention comprises: a variable transmission rule map unit for setting a transmission rule with a variable block length and a variable block interval as a unit of memory transmission rule; a direct memory access unit for sending data line of the variable block length and the variable block interval, in case of access to the unit of memory by using the unit of memory transmission rule determined by the variable transmission rule map unit; and an interface unit for retrieving the unit of memory transmission rule, which is necessary for sending the data line of the variable block length and the variable block interval, from the variable transmission rule map unit and sending the unit of memory transmission rule to the direct memory access unit.

摘要翻译： 提供了直接存储器访问装置和直接存储器访问方法。 本发明的直接存储器访问装置包括：可变传输规则映射单元，用于将具有可变块长度的传输规则和可变块间隔设置为存储器传输规则的单元; 在通过使用由可变传输规则映射单元确定的存储器发送规则的单元访问存储器单元的情况下，发送可变块长度和可变块间隔的数据线的直接存储器存取单元; 以及用于从可变传输规则映射单元检索用于发送可变块长度和可变块间隔的数据线所必需的存储器传输规则单元的接口单元，并将存储器传输规则单元发送到直接 存储器存取单元。

公开(公告)号：US06421341B1

公开(公告)日：2002-07-16

申请号：US09173018

申请日：1998-10-15

申请人： Il Song Han ,  Young Jae Choi ,  Dae Hwan Kim

发明人： Il Song Han ,  Young Jae Choi ,  Dae Hwan Kim

IPC分类号： H04L1250

CPC分类号： H04L49/101 ,  H04L2012/5686

摘要： This invention relates to a high speed packet switching controller in a telephone switching system which can suitably be applied to a packet controller having large capacity using a neural network chip and maximize the system performance by the optimized switching operation. The high speed packet switching controller comprises a row address decoder for decoding a weight raw address which is inputted thereto, a column address decoder for decoding a weight column address which is inputted thereto, a matrix array for providing the neural network using address signals provided from the row address decoder and column address decoder and outputing varied voltage in accordance with an external weight value, a neural network for producing a final crossbar switching control signal, an external input/output bus for transmitting an output signal of the neural network, and an internal neural data bus for transmitting the address signal output from the row address decoder and column address decoder to the matrix array.

摘要翻译： 本发明涉及电话交换系统中的高速分组交换控制器，其可以适用于使用神经网络芯片的具有大容量的分组控制器，并且通过优化的切换操作使系统性能最大化。 高速分组交换控制器包括：行地址解码器，用于对输入的加权原始地址进行解码;列地址解码器，用于对输入的加权列地址进行解码;矩阵阵列，用于使用从 行地址解码器和列地址解码器，并根据外部权重值输出变化的电压，用于产生最终交叉开关控制信号的神经网络，用于发送神经网络的输出信号的外部输入/输出总线，以及 用于将从行地址解码器和列地址解码器输出的地址信号发送到矩阵阵列的内部神经数据总线。

公开(公告)号：US5920212A

公开(公告)日：1999-07-06

申请号：US941105

申请日：1997-09-30

申请人： Il Song Han

发明人： Il Song Han

IPC分类号： G06G7/28 ,  G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  H03K4/06

CPC分类号： G06N3/0635

摘要： Control-type continuous ramp converting apparatus and method therefore. The present invention provides real-time processing of neurons in the neural network, easy implementation and reduction of manufacture cost of high density neurons in the neural network. The present invention comprises a first voltage controlling part for receiving a first voltage from an outside, and for non-linearly increasing a charged voltage in accordance with a differential continuous function of an exponential function; a second voltage controlling part for receiving a second voltage from an outside, and for non-linearly reducing a charged voltage in accordance with a differential continuous function of an exponential function; a charging part for charging an input current, and for providing the charged voltage of the charging part with the second voltage controlling part and an outside; and a plurality of switches for coupling outside and the first and the second voltage controlling part to the charging part, for selectively providing a third voltage from outside, an increased voltage and a decreased voltage based on the voltage of the charging part.

摘要翻译： 因此，控制式连续斜升变换装置和方法。 本发明提供神经网络中神经元的实时处理，容易实现和降低神经网络中高密度神经元的制造成本。 本发明包括：第一电压控制部分，用于从外部接收第一电压，并且根据指数函数的差分连续函数非线性地增加充电电压; 第二电压控制部分，用于从外部接收第二电压，并且根据指数函数的差分连续函数非线性地减小充电电压; 用于对输入电流进行充电的充电部分，以及用于将充电部分的充电电压提供给第二电压控制部分和外部; 以及用于耦合到外部的多个开关和第一和第二电压控制部分到充电部分，用于基于充电部分的电压选择性地从外部提供第三电压，增加的电压和降低的电压。

公开(公告)号：US20100191918A1

公开(公告)日：2010-07-29

申请号：US12651918

申请日：2010-01-04

申请人： Hwang-Soo Lee ,  Jung-Keum Kim ,  Il-Song Han ,  Young Serk Shim

发明人： Hwang-Soo Lee ,  Jung-Keum Kim ,  Il-Song Han ,  Young Serk Shim

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： Disclosed are a cache controller device, an interfacing method and a programming method using the same. The cache controller device prefetching and supplying data distributed in a memory to a main processor, includes: a cache temporarily storing data in a memory block having a limited size; a cache controller circularly reading out the data from the memory block to a cache memory, or transferring the data from the cache memory to the cache; and a memory input/output controller controlling prefetching the data to the cache, or transferring the data from the cache to a memory.

摘要翻译： 公开了一种高速缓存控制器设备，接口方法和使用该方法的编程方法。 高速缓存控制器设备将分配在存储器中的数据预取并提供给主处理器，包括：高速缓冲存储器将数据临时存储在具有有限尺寸的存储器块中; 高速缓存控制器循环地从存储器块读出数据到高速缓冲存储器，或者将数据从高速缓冲存储器传送到高速缓存; 以及控制器将数据预取到高速缓存的存储器输入/输出控制器，或将数据从高速缓存传送到存储器。