公开(公告)号：US20160190142A1

公开(公告)日：2016-06-30

申请号：US15061038

申请日：2016-03-04

申请人： Ju-Youn Kim ,  Sang-Duk Park ,  Jae-Kyung Seo ,  Kwang-Sub Yoon ,  In-Gu Yoon

发明人： Ju-Youn Kim ,  Sang-Duk Park ,  Jae-Kyung Seo ,  Kwang-Sub Yoon ,  In-Gu Yoon

IPC分类号： H01L27/11 ,  H01L21/266 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/1104 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545

摘要： In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

摘要翻译： 在制造半导体器件的方法中，第一栅电极和第二栅电极分别设置在衬底上，第一栅极电极和第二栅电极分别形成在衬底的第一区域和第二区域中。 导电缓冲层沿着第一栅电极和第二栅电极的侧壁以及第一栅电极和第二栅电极的上表面形成。 形成覆盖缓冲层上的基板的第一区域的第一掩模图案。 使用第一掩模图案作为离子注入工艺的掩模，在第二栅电极的侧面的衬底中形成第一杂质区。

公开(公告)号：US07560765B2

公开(公告)日：2009-07-14

申请号：US11624464

申请日：2007-01-18

申请人： Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

发明人： Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on the semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be electrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

摘要翻译： 非易失性存储器件包括半导体衬底; 源区域，其形成在所述半导体衬底中; 形成为与半导体衬底上的源极区域重叠的栅极绝缘膜; 形成在所述栅极绝缘膜上的浮栅，以具有在与所述源极区重叠的部分中形成均匀电场的结构; 形成为从浮置栅极的上部的浮动栅极的一个侧壁电绝缘的控制栅极，插入在浮置栅极和控制栅极之间的栅极间绝缘膜，以及漏极区域 其形成为与控制栅极的另一侧相邻。

公开(公告)号：US20070048924A1

公开(公告)日：2007-03-01

申请号：US11505355

申请日：2006-08-17

申请人： In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

发明人： In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

摘要翻译： 制造非易失性存储器件的方法可以包括在半导体衬底上形成分离的浮置栅极，在半导体衬底上形成控制栅极，在半导体衬底的表面上保形地形成缓冲膜，将离子注入半导体衬底 浮置栅极，形成与各对浮置栅极的每个浮置栅极部分重叠的共同源极区域，在缓冲膜上沉积绝缘膜，在浮置栅极和控制栅极的侧壁处蚀刻缓冲膜和绝缘膜 在浮置栅极和控制栅极的侧壁处形成间隔物，并且在除了形成公共源极区域的控制栅极的一侧之外的控制栅极的一侧的半导体衬底中形成漏极区域。

公开(公告)号：US20050064661A1

公开(公告)日：2005-03-24

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20140370672A1

公开(公告)日：2014-12-18

申请号：US14169608

申请日：2014-01-31

申请人： Ju-Youn Kim ,  Sang-Duk Park ,  Jae-Kyung Seo ,  Kwang-Sub Yoon ,  In-Gu Yoon

发明人： Ju-Youn Kim ,  Sang-Duk Park ,  Jae-Kyung Seo ,  Kwang-Sub Yoon ,  In-Gu Yoon

IPC分类号： H01L21/8238

CPC分类号： H01L27/1104 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545

摘要： In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

摘要翻译： 在制造半导体器件的方法中，第一栅电极和第二栅电极分别设置在衬底上，第一栅极电极和第二栅电极分别形成在衬底的第一区域和第二区域中。 导电缓冲层沿着第一栅电极和第二栅电极的侧壁以及第一栅电极和第二栅电极的上表面形成。 形成覆盖缓冲层上的基板的第一区域的第一掩模图案。 使用第一掩模图案作为离子注入工艺的掩模，在第二栅电极的侧面的衬底中形成第一杂质区。

公开(公告)号：US07553726B2

公开(公告)日：2009-06-30

申请号：US11505355

申请日：2006-08-17

申请人： In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

发明人： In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

摘要翻译： 制造非易失性存储器件的方法可以包括在半导体衬底上形成分离的浮置栅极，在半导体衬底上形成控制栅极，在半导体衬底的表面上保形地形成缓冲膜，将离子注入半导体衬底 浮置栅极，形成与各对浮置栅极的每个浮置栅极部分重叠的共同源极区域，在缓冲膜上沉积绝缘膜，在浮置栅极和控制栅极的侧壁处蚀刻缓冲膜和绝缘膜 在浮置栅极和控制栅极的侧壁处形成间隔物，并且在除了形成公共源极区域的控制栅极的一侧之外的控制栅极的一侧的半导体衬底中形成漏极区域。

公开(公告)号：US07375391B2

公开(公告)日：2008-05-20

申请号：US11246590

申请日：2005-10-11

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US07205194B2

公开(公告)日：2007-04-17

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20060027858A1

公开(公告)日：2006-02-09

申请号：US11246590

申请日：2005-10-11

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US20050063208A1

公开(公告)日：2005-03-24

申请号：US10840803

申请日：2004-05-07

申请人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

发明人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

IPC分类号： H01L21/8247 ,  G11C11/42 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

摘要翻译： 提供了使用间隔物氧化工艺制造分裂栅极闪存单元的方法。 在浮栅层上形成氧化阻挡层，在氧化阻挡层中形成露出浮栅的一部分的开口。 随后，通过氧化形成具有绝缘性的材料层的开口的侧壁上的间隔物，并且在开口中形成浮栅和控制栅之间的栅间氧化层图案，同时通过执行 氧化过程。