-
1.发明申请公开(公告)号：US20100175042A1
公开(公告)日：2010-07-08
申请号：US12349104
申请日：2009-01-06
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705
摘要： The present invention relates to the modeling of lithographic processes for use in the design of photomasks for the manufacture of semiconductor integrated circuits, and particularly to the modeling of the complex effects due to interaction of the illuminating light with the mask topography. According to the invention, an isofield perturbation to a thin mask representation of the mask is provided by determining, for the components of the illumination, differences between the electric field on a feature edge having finite thickness and on the corresponding feature edge of a thin mask representation. An isofield perturbation is obtained from a weighted coherent combination of the differences for each illumination polarization. The electric field of a mask having topographic edges is represented by combining a thin mask representation with the isofield perturbation applied to each edge of the mask.
摘要翻译： 本发明涉及用于制造半导体集成电路的光掩模设计中使用的光刻工艺的建模，特别涉及由于照明光与掩模形貌的相互作用引起的复杂效应的建模。 根据本发明，通过确定对于照明的组分，具有有限厚度的特征边缘上的电场与薄掩模的相应特征边缘之间的差异来确定对掩模的薄掩模表示的异场扰动 表示。 从每个照明偏振的差的加权相干组合获得异场扰动。 通过将薄掩模表示与应用于掩模的每个边缘的异场扰动组合来表示具有形貌边缘的掩模的电场。
-
2.发明授权公开(公告)号：US07607114B2
公开(公告)日：2009-10-20
申请号：US11778302
申请日：2007-07-16
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译： 通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。 该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束 特征对其他层的影响。 该方法可以在用于在计算机系统上执行的计算机程序产品中实现。 所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。
-
3.发明申请METHOD OF CONFLICT AVOIDANCE IN FABRICATION OF GATE-SHRINK ALTERNATING PHASE SHIFTING MASKS 失效闸门相互替换相变掩模制造中的冲突避免方法公开(公告)号：US20050175906A1
公开(公告)日：2005-08-11
申请号：US10708055
申请日：2004-02-05
申请人： Lars Liebmann , Ioana Graur
发明人： Lars Liebmann , Ioana Graur
CPC分类号： G03F1/30
摘要： A method of designing a layout of an alternating phase shifting mask for projecting an image of an integrated circuit design having a plurality of features to be projected using alternating phase shifting segments, including a gate-shrink region of a transistor having a critical width along a length thereof that extends beyond a diffusion region. The method also provides alternating phase shift design rules based on alternating phase shift design parameters comprising minimum phase width, minimum phase-to-phase spacing, and minimum extension of critical width beyond another feature. The method then includes identifying portions of the integrated circuit layout having a critical width feature that violate the alternating phase shift design rules, and reducing the length that the critical width gate-shrink region feature extends beyond the other diffusion region feature to the minimum extension. An alternating phase shifting mask layout is then generated in conformance with the alternating phase shift design rules.
摘要翻译： 一种设计交替相移掩模的布局的方法，用于使用交变相移段来投影具有要投影的多个特征的集成电路设计的图像，所述交变相移段包括沿着沿着具有临界宽度的晶体管的栅极 - 收缩区域 其长度延伸超过扩散区域。 该方法还提供基于交替相移设计参数的交替相移设计规则，其包括最小相位宽度，最小相间间隔以及临界宽度超出另一特征的最小延伸。 该方法然后包括识别具有违反交替相移设计规则的临界宽度特征的集成电路布局的部分，并且减小临界宽度栅 - 收缩区域特征延伸超出另一扩散区域特征到最小延伸的长度。 然后根据交变相移设计规则生成交替的相移掩模布局。
-
公开(公告)号：US07650587B2
公开(公告)日：2010-01-19
申请号：US11564957
申请日：2006-11-30
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.
摘要翻译： 提供了一种用于设计用于制造集成电路的掩模的方法，其中需要诸如用于交替相移，双曝光和双曝光蚀刻掩模的着色的掩模布局被组织成无色层级设计单元。 在OPC修改之前，每个分层设计单元都是局部有色的。 然后在本地着色的分层设计单元上执行OPC。 可以丢弃用于分层布置的OPC修改的设计单元的局部着色信息。 在OPC修改之后，未着色的OPC修改的设计单元可以放置在掩模布局内，并且扁平化的数据可能被着色。 因此，掩模设计的周转时间显着提高，因为对分层数据执行数字密集的OPC，避免了对平坦化数据执行OPC的需要，而对扁平化数据执行的密集型全局着色较少。
-
公开(公告)号：US20070261013A1
公开(公告)日：2007-11-08
申请号：US11778302
申请日：2007-07-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
-
公开(公告)号：US06795961B2
公开(公告)日：2004-09-21
申请号：US10430148
申请日：2003-05-06
申请人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Young O. Kim
发明人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Young O. Kim
IPC分类号： G06F1750
CPC分类号： G03F1/30
摘要： A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.
摘要翻译： 描述了一种方法和计算机程序产品，用于优化根据规则层级将二进制属性分配给设计元素的电路布局的设计。 例如，交替相移掩模（altPSM）的设计首先根据规定分配相位形状的规则进行优化，该相位形状使关键电路元件的图像质量最大化，然后进一步优化以最小化掩模可制造性问题，而不会显着增加设计的复杂性 工艺流程。 根据附加规则进一步优化设计可以按顺序降低的优先顺序执行。 由于规则的优先级减少，只要优先级较高的规则不被侵犯，某些违反较低优先权规则就可以接受。
-
公开(公告)号：US07860701B2
公开(公告)日：2010-12-28
申请号：US11942309
申请日：2007-11-19
申请人： Ioana Graur , Kafai Lai , Rama N. Singh
发明人： Ioana Graur , Kafai Lai , Rama N. Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.
摘要翻译： 一种用于预测光刻印刷在晶片上的集成电路片段的功能性的方法。 最初提供了集成电路的二维设计，包括具有临界宽度的集成电路段，并且模拟了临界宽度集成电路段的二维打印图像。 该方法然后包括确定设计的关键宽度集成电路段的周长或区域与模拟的打印临界宽度集成电路段的比率，以及基于周边或区域的比率来预测打印之后的临界宽度集成电路段的功能。
-
8.发明申请Method and System for Obtaining Bounds on Process Parameters for OPC-Verification 有权用于获取OPC验证过程参数边界的方法和系统公开(公告)号：US20090123057A1
公开(公告)日：2009-05-14
申请号：US11937073
申请日：2007-11-08
IPC分类号： G06K9/00
CPC分类号： G06K9/036 , G03F7/70441
摘要： Embodiments of the present invention provide a method of performing printability verification of a mask layout. The method includes creating one or more tight clusters; computing a set of process parameters associated with a point on said mask; comparing said set of process parameters to said one or more tight clusters; and reporting an error when at least one of said process parameters is away from said one or more tight clusters.
摘要翻译： 本发明的实施例提供了一种执行掩模布局的可印刷性验证的方法。 该方法包括创建一个或多个紧密簇; 计算与所述掩模上的点相关联的一组过程参数; 将所述一组过程参数与所述一个或多个紧密簇进行比较; 并且当至少一个所述过程参数远离所述一个或多个紧密簇时报告错误。
-
公开(公告)号：US20080134130A1
公开(公告)日：2008-06-05
申请号：US11564957
申请日：2006-11-30
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.
摘要翻译： 提供了一种用于设计用于制造集成电路的掩模的方法，其中需要诸如用于交替相移，双曝光和双曝光蚀刻掩模的着色的掩模布局被组织成无色层级设计单元。 在OPC修改之前，每个分层设计单元都是局部有色的。 然后在本地着色的分层设计单元上执行OPC。 可以丢弃用于分层布置的OPC修改的设计单元的局部着色信息。 在OPC修改之后，未着色的OPC修改的设计单元可以放置在掩模布局内，并且扁平化的数据可能被着色。 因此，掩模设计的周转时间显着提高，因为对分层数据执行数字密集型OPC，避免了对平坦化数据执行OPC的需要，而对扁平化数据执行的密集型全局着色较少。
-
公开(公告)号：US07305334B2
公开(公告)日：2007-12-04
申请号：US10908724
申请日：2005-05-24
申请人： Ioana Graur , Kafai Lai , Rama N. Singh
发明人： Ioana Graur , Kafai Lai , Rama N. Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.
摘要翻译： 一种用于预测光刻印刷在晶片上的集成电路片段的功能性的方法。 最初提供了集成电路的二维设计，包括具有临界宽度的集成电路段，并且模拟了临界宽度集成电路段的二维打印图像。 该方法然后包括确定设计的关键宽度集成电路段的周长或区域与模拟的打印临界宽度集成电路段的比率，以及基于周边或区域的比率来预测打印之后的临界宽度集成电路段的功能。
-
-
-
-
-
-
-
-
-
搜索结果
40 条记录 (耗时 0.014 秒)