公开(公告)号：US08822278B2

公开(公告)日：2014-09-02

申请号：US13434128

申请日：2012-03-29

Applicant: Josephine B. Chang ,  Chung-Hsun Lin ,  Isaac Lauer ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Chung-Hsun Lin ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/1203

Abstract: Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided.

Abstract translation: 提供了非对称FET器件及其制造方法，其采用可变间距栅极。 一方面，一种用于制造FET器件的方法包括以下步骤。 提供晶片。 使用STI在晶片中形成多个有效区域。 在晶片上形成多个栅极堆叠，其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少给定的一个有源区域，给定的源极侧的栅极到栅极间隔 有源面积大于给定有源区域的漏极侧上的栅极至栅极间距。 隔板形成在栅极堆叠的相对侧上。 在给定活动区域的源侧执行成角度的植入物。 还提供了FET器件。

公开(公告)号：US20140239258A1

公开(公告)日：2014-08-28

申请号：US13571657

申请日：2012-08-10

Applicant: Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

Inventor： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/0847 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S977/723 ,  Y10S977/938

Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

Abstract translation: 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。

公开(公告)号：US08723162B2

公开(公告)日：2014-05-13

申请号：US13541022

申请日：2012-07-03

Applicant: Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

Inventor： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

Abstract translation: 纳米线隧道场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有第一远端和第二远端的硅部分，硅部分被围绕硅部分周向设置的栅极结构围绕，漏极区域包括 从第一远端延伸的掺杂硅部分，布置在沟道区域中的掺杂硅部分的一部分，由硅部分的第二远端限定的空腔和栅极结构的内径，以及源区域， 从空腔中的硅部分的第二远端外延延伸的掺杂外延硅部分，第一焊盘区域和硅衬底的一部分。

公开(公告)号：US08673731B2

公开(公告)日：2014-03-18

申请号：US13589707

申请日：2012-08-20

Applicant: Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/1203

Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.

Abstract translation: 提供了使用功能函数设置材料来减小平面CMOS器件中的短通道效应的门功能工程技术。 一方面，制造CMOS器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在其上具有沟槽的晶片上形成有图案的电介质，其中将形成栅叠层。 在每个沟槽中沉积：（i）共形栅极电介质（ii）共形栅极金属层和（iii）共形功函数设定金属层。 沉积到给定的一个沟槽中的保形栅极金属层的体积和/或共形功函设定金属层的体积与在给定沟槽中形成的栅极堆叠的长度成比例。 还提供了CMOS器件。

公开(公告)号：US08658518B1

公开(公告)日：2014-02-25

申请号：US13588724

申请日：2012-08-17

Applicant: Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L29/16 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.

Abstract translation: 制造纳米线FET器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 围绕每个纳米线形成界面氧化物。 共形栅电介质沉积在界面氧化物上。 保形第一栅极材料沉积在保形栅极电介质上。 工件功能设定材料沉积在保形第一栅极材料上。 第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。 栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。

公开(公告)号：US20140051225A1

公开(公告)日：2014-02-20

申请号：US13589707

申请日：2012-08-20

Applicant: Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L21/76

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/1203

Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.

Abstract translation: 提供了使用功能函数设置材料来减小平面CMOS器件中的短通道效应的门功能工程技术。 一方面，制造CMOS器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在其上具有沟槽的晶片上形成有图案的电介质，其中将形成栅叠层。 在每个沟槽中沉积：（i）共形栅极电介质（ii）共形栅极金属层和（iii）共形功函数设定金属层。 沉积到给定一个沟槽中的保形栅极金属层的体积和/或共形功函设定金属层的体积与在给定沟槽中形成的栅极堆叠的长度成比例。 还提供了CMOS器件。

公开(公告)号：US08617957B1

公开(公告)日：2013-12-31

申请号：US13607877

申请日：2012-09-10

Applicant: Josephine B Chang ,  Gen Pei Lauer ,  Isaac Lauer ,  Jeffrey W Sleight

Inventor： Josephine B Chang ,  Gen Pei Lauer ,  Isaac Lauer ,  Jeffrey W Sleight

IPC: H01L21/331

CPC classification number: H01L29/42304 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735 ,  H01L29/785

Abstract: A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.

Abstract translation: 一种制造双极晶体管器件的方法。 该方法包括以下步骤：提供其上具有硅层的SOI衬底; 在硅层上平版印刷鳍状硬掩模; 将虚拟接触线放置在图案化翅片硬掩模的中心部分上; 掺杂集电极/发射极区域; 在所述集电极区域和所述发射极区域上沉积填充层; 去除虚拟接触线以露出沟槽和图案化散热片硬掩模的中心部分; 在除去虚拟接触线的步骤之后，通过在沟槽内去除未被图案化翅片硬掩模的中心部分覆盖的硅层的一部分来形成翅片形基底区域; 掺杂鳍片状基底区域; 以及通过在所述鳍状基极区域上的接触线材料填充所述沟槽而形成接触线，其中所述集电极/发射极区域与所述接触线自对准。

公开(公告)号：US20130264614A1

公开(公告)日：2013-10-10

申请号：US13611387

申请日：2012-09-12

Applicant: Isaac Lauer ,  Effendi Leobandung ,  Ghavam G. Shahidi

Inventor： Isaac Lauer ,  Effendi Leobandung ,  Ghavam G. Shahidi

IPC: H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method for forming a semiconductor device includes forming a gate stack on a monocrystalline substrate. A surface of the substrate adjacent to the gate stack and below a portion of the gate stack is amorphorized. The surface is etched to selectively remove a thickness of amorphorized portions to form undercuts below the gate stack. A layer is epitaxially grown in the thickness and the undercuts to form an extension region for the semiconductor device. Devices are also provided.

公开(公告)号：US08536041B2

公开(公告)日：2013-09-17

申请号：US13559182

申请日：2012-07-26

Applicant: Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

Inventor： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract translation: 提供了一种用于制造晶体管的方法。 该晶体管包括一个硅层，该硅层包括一个源区和一个漏极区，一个位于源极区和漏极区之间的硅层上的栅极堆叠，以及设置在栅叠层的侧壁上的侧壁隔离层。 栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。 还提供了制造这种晶体管的方法。

公开(公告)号：US08530932B2

公开(公告)日：2013-09-10

申请号：US13425654

申请日：2012-03-21

Applicant: Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

IPC: H01L31/109 ,  H01L31/0328

CPC classification number: H01L29/7391 ,  H01L29/66356

Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

Abstract translation: 一种半导体制造方法，包括在基板上沉积虚拟栅极层，图案化虚拟栅极层，在伪栅极层上沉积硬掩模层，图案化硬掩模层，在凹模栅极层附近蚀刻到衬底中的凹陷， 将半导体材料进入凹部，去除硬掩模层，将替代间隔物沉积到伪栅极层上，在伪栅极层和替换间隔物上进行氧化物沉积，去除伪栅极和替换间隔物，从而在氧化物中形成栅极凹槽， 将栅极堆叠沉积到凹槽中。