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    Reliable Memory Mapping In A Computing System
    1.
    发明申请
    Reliable Memory Mapping In A Computing System 审中-公开
    计算系统中可靠的内存映射

    公开(公告)号：US20130117493A1

    公开(公告)日：2013-05-09

    申请号：US13289311

    申请日：2011-11-04

    申请人： Nathan C. Skalsky ,  Ivan R. Zapata

    发明人： Nathan C. Skalsky ,  Ivan R. Zapata

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0646

    摘要： Methods, apparatus, and products for reliable memory mapping in a computing system, the computing system including a plurality of memory modules, including: determining, by a channel mapping module, a reliability rating for each of a plurality of memory controller address ranges; mapping, by the channel mapping module, critical system-level memory addresses to the most reliable memory controller address ranges; and directing, by the channel mapping module, memory accesses addressed to a critical system-level memory address to the most reliable memory controller address ranges.

    摘要翻译： 用于在计算系统中可靠存储器映射的方法，装置和产品，所述计算系统包括多个存储器模块，所述计算系统包括：由信道映射模块确定多个存储器控制器地址范围中的每一个的可靠性等级; 通过映射模块将关键系统级内存地址映射到最可靠的存储器控​​制器地址范围; 并且通过信道映射模块将寻址到关键系统级存储器地址的存储器访问引导到最可靠的存储器控​​制器地址范围。

    Administering computing system resources in a computing system
    3.
    发明授权
    Administering computing system resources in a computing system 有权
    管理计算系统中的计算系统资源

    公开(公告)号：US08495269B2

    公开(公告)日：2013-07-23

    申请号：US13529217

    申请日：2012-06-21

    申请人： Mark A. Brandyberry ,  Todd W. Justus ,  Paul D. Kangas ,  Brent W. Yardley ,  Ivan R. Zapata

    发明人： Mark A. Brandyberry ,  Todd W. Justus ,  Paul D. Kangas ,  Brent W. Yardley ,  Ivan R. Zapata

    IPC分类号： G06F9/02 ,  H05K7/20

    CPC分类号： G06F1/20 ,  G06F1/185

    摘要： Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

    摘要翻译： 在计算系统中管理计算系统资源，所述计算系统包括适于接收具有一组引脚的电气部件的至少一个插槽，所述插槽被配置为将安装在所述插槽内的所述电气部件的引脚耦合到所述计算系统 存在可检测的挡板包括具有与电气部件一致的形状因数的无源底板和连接到被动底盘的存在可检测引脚组，该引脚与电部件一致，包括：由系统管理器识别， 存在可检测的挡板; 并且由系统管理员根据存在的可检测的挡板属性来管理计算系统的操作属性。

    Operating processor below maximum turbo mode frequency by sending higher than actual current amount signal to monitor
    4.
    发明授权
    Operating processor below maximum turbo mode frequency by sending higher than actual current amount signal to monitor 失效
    通过发送高于实际电流量信号进行监控，操作处理器低于最大涡轮模式频率

    公开(公告)号：US08429441B2

    公开(公告)日：2013-04-23

    申请号：US12762419

    申请日：2010-04-19

    申请人： Brian A. Baker ,  Justin P. Bandholz ,  William H. Cox, Jr. ,  Sumeet Kochar ,  Ivan R. Zapata

    发明人： Brian A. Baker ,  Justin P. Bandholz ,  William H. Cox, Jr. ,  Sumeet Kochar ,  Ivan R. Zapata

    IPC分类号： G06F1/04

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  Y02D10/126

    摘要： A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the processor by over-reporting the amount of current drawn by the processor to the current monitoring feedback line to the processor, wherein the processor uses the over-reported current to maintain operation of the processor within performance specifications of the processor. An automatic calibration routine may be used to determine nominal amounts of current over-reporting that may be used to prevent the processor performance from exceeding the maximum turbo mode. In one embodiment, a digital potentiometer is included in the voltage regulator circuit to over-report the current as instructed.

    摘要翻译： 一种用于在涡轮增压状态下控制处理器的最大涡轮模式的方法，计算机程序产品和系统。 该方法包括通过将由处理器提取的电流量过度报告给处理器的当前监视反馈线来限制处理器可用的最大涡轮模式，其中处理器使用过度报告的电流来维持处理器的操作 处理器的性能规格。 可以使用自动校准程序来确定可用于防止处理器性能超过最大涡轮模式的当前过度报告的标称量。 在一个实施例中，数字电位计被包括在电压调节器电路中以按指示过度报告电流。

    Preemptive Thermal Management For A Computing System Based On Cache Performance
    6.
    发明申请
    Preemptive Thermal Management For A Computing System Based On Cache Performance 有权
    基于缓存性能的计算系统的先发热管理

    公开(公告)号：US20090164852A1

    公开(公告)日：2009-06-25

    申请号：US11960599

    申请日：2007-12-19

    申请人： Challis L. Purrington ,  Michael L. Scollard ,  Victor A. Stankevich ,  Ivan R. Zapata

    发明人： Challis L. Purrington ,  Michael L. Scollard ,  Victor A. Stankevich ,  Ivan R. Zapata

    IPC分类号： G06F11/07

    CPC分类号： G06F1/206

    摘要： Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of memory contents of the cached computer memory, that include: attempting, by the processor, to retrieve portions of the memory contents of the cached computer memory from the processor cache, resulting in cache misses for the processor cache; tracking, by the processor, cache miss statistics for the processor cache in the computing system, the cache miss statistics describing the cache misses for the processor cache; and administering a thermal management device for the computing system in dependence upon the cache miss statistics, the thermal management device operatively coupled to the processor and capable of managing temperature for the computing system.

    摘要翻译： 公开了用于基于高速缓存性能的计算系统的先占热管理的方法，装置和产品，所述计算系统具有处理器，可操作地耦合到所述处理器的高速缓存计算机存储器，以及可操作地耦合到所述处理器的处理器高速缓存器 能够存储缓存的计算机存储器的存储器内容的子集，其包括：由处理器尝试从处理器高速缓存中检索缓存的计算机存储器的存储器内容的部分，导致处理器高速缓存的高速缓存未命中; 由处理器跟踪计算系统中处理器缓存的高速缓存未命中统计信息，描述处理器高速缓存未命中的高速缓存未命中统计信息; 以及根据所述高速缓存未命中统计管理所述计算系统的热管理装置，所述热管理装置可操作地耦合到所述处理器并能够管理所述计算系统的温度。

    Memory Training Results Corresponding To A Plurality Of Memory Modules
    7.
    发明申请
    Memory Training Results Corresponding To A Plurality Of Memory Modules 有权
    内存培训结果对应于多个内存模块

    公开(公告)号：US20130159687A1

    公开(公告)日：2013-06-20

    申请号：US13332092

    申请日：2011-12-20

    申请人： William H. Cox, JR. ,  Jimmy G. Foster, SR. ,  Sumeet Kochar ,  Ivan R. Zapata

    发明人： William H. Cox, JR. ,  Jimmy G. Foster, SR. ,  Sumeet Kochar ,  Ivan R. Zapata

    IPC分类号： G06F15/177

    CPC分类号： G06F12/0646 ,  G06F11/3051 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    摘要： Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

    摘要翻译： 提供了用于改善对应于多个存储器模块的存储器训练结果的方法，装置和计算机程序产品。 实施例包括在启动包括多个存储器模块的系统的引导顺序时检测硬件配置变化; 产生多个训练迭代，对应于数据选通（DQS）信号与所述多个存储器模块的数据有效数据（DQ）行窗口的对准的参考训练值; 识别每个训练迭代，为该训练迭代生成的参考训练值内的任何外部值; 从参考训练值中消除所识别的外部值; 基于剩余参考训练值的平均值生成最终参考训练值; 并使用最终参考训练值作为系统引导顺序的DQ-DQS定时值。

    Fall time accelerator circuit
    10.
    发明授权
    Fall time accelerator circuit 有权
    下降时间加速器电路

    公开(公告)号：US07992030B2

    公开(公告)日：2011-08-02

    申请号：US11746102

    申请日：2007-05-09

    申请人： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

    发明人： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

    IPC分类号： G06F1/00

    CPC分类号： H03K5/1534 ,  H03K19/01721

    摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.

    摘要翻译： 本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。 在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。 下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。 电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。 最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。