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    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    集成电路装置及其制造方法

    公开(公告)号：US20160133632A1

    公开(公告)日：2016-05-12

    申请号：US14853442

    申请日：2015-09-14

    申请人： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

    发明人： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

    IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L27/092

    CPC分类号： H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

    摘要： A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

    摘要翻译： 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities
    3.
    发明申请
    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities 有权
    使用具有高应力特性的绝缘层的CMOS集成电路的形成方法来改善NMOS和PMOS晶体管载体的迁移率

    公开(公告)号：US20090124093A1

    公开(公告)日：2009-05-14

    申请号：US12353519

    申请日：2009-01-14

    申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    IPC分类号： H01L21/469

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

    摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

    Methods for forming damascene wiring structures having line and plug conductors formed from different materials
    4.
    发明授权
    Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
    用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法

    公开(公告)号：US07514354B2

    公开(公告)日：2009-04-07

    申请号：US11323328

    申请日：2005-12-30

    申请人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    发明人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

    摘要翻译： 提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。 例如，形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。 然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域 。 然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

    Nickel salicide process with reduced dopant deactivation
    6.
    发明授权
    Nickel salicide process with reduced dopant deactivation 有权
    具有减少掺杂剂钝化的镍硅化物工艺

    公开(公告)号：US07232756B2

    公开(公告)日：2007-06-19

    申请号：US10812003

    申请日：2004-03-30

    申请人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

    发明人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.

    摘要翻译： 提供了形成在硅化物阻挡层（SBL）完成之后形成的在低于约700℃的温度下形成的硅化物层的半导体器件（例如硅化镍）的示例性方法。 SBL的形成倾向于使栅极，轻掺杂漏极和/或源极/漏极区域中的掺杂物质失活。 示例性方法包括后SBL激活退火，代替传统的植入物后激活退火或替代传统的植入后激活退火。 后SBL退火的使用产生具有反映充分掺杂剂的再活化以克服SBL工艺效应的性质的CMOS晶体管，同时允许使用较低温度的硅化物，包括硅化镍，特别是掺入较小部分的硅化镍 合金金属如钽，表现出减少的团聚和改善的温度稳定性。

    Methods of fabricating a semiconductor device having MOS transistor with strained channel
    9.
    发明授权
    Methods of fabricating a semiconductor device having MOS transistor with strained channel 有权
    制造具有应变通道的MOS晶体管的半导体器件的方法

    公开(公告)号：US07084061B2

    公开(公告)日：2006-08-01

    申请号：US10799788

    申请日：2004-03-12

    申请人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sun-Pil Youn ,  Min-Joo Kim ,  Kwan-Jong Roh

    发明人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sun-Pil Youn ,  Min-Joo Kim ,  Kwan-Jong Roh

    IPC分类号： H01L21/44

    CPC分类号： H01L29/7843 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.

    摘要翻译： 提供了制造具有具有应变通道的MOS晶体管的半导体器件的方法。 该方法包括在半导体衬底的一部分处形成MOS晶体管。 MOS晶体管形成为具有彼此间隔开的源极/漏极区域和位于源极/漏极区域之间的沟道区域上方的栅极电极。 在具有MOS晶体管的半导体衬底上形成应力层。 然后应力层退火以将应力层的物理应力转变为拉伸应力或增加应力层的拉伸应力。