公开(公告)号：US07971168B1

公开(公告)日：2011-06-28

申请号：US12128919

申请日：2008-05-29

申请人： Robert Swanson ,  Jacob Avidan ,  Roger Carpenter

发明人： Robert Swanson ,  Jacob Avidan ,  Roger Carpenter

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e.g., impact to schedule, CPU/memory resources, ECOs).

摘要翻译： 在各种实施例中，重复块的每个可能的不同实例可以被同时优化用于定时。 重复块的每个实例可以被视为模式，诸如功能模式或测试模式，允许同时执行实现计算。 使用多模时序分析，可以同时分析和优化重复块的所有实例。 基于多模式分析，重复块的实例可以相同地或基本相似地实现，这可以降低与多次实现相同块相关联的成本（例如，对调度，CPU /存储器资源，ECO的影响）。

公开(公告)号：US06536028B1

公开(公告)日：2003-03-18

申请号：US09525184

申请日：2000-03-14

申请人： Athanassios Katsioulas ,  Stan Chow ,  Jacob Avidan ,  Dimitris Fotakis

发明人： Athanassios Katsioulas ,  Stan Chow ,  Jacob Avidan ,  Dimitris Fotakis

IPC分类号： G06F1750

CPC分类号： G06F17/5068 ,  G06F2217/66

摘要： A STANDARD BLOCK architecture for integrated circuit (IC) design. The STANDARD BLOCK architecture provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures. The STANDARD BLOCK architecture includes a STANDARD BLOCK form that is physically constrained having one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCK granularity is larger than the standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells. In the STANDARD BLOCK architecture, each STANDARD BLOCK has flexible physical design properties. In this design style, the STANDARD BLOCKs are provided as general physical abstractions such that each STANDARD BLOCK is akin to a black box model with the majority of its internal design aspects invisible to the top-level assembly tool while selected design aspects remain visible. The global design aspects of each STANDARD BLOCK include its fundamental architectural and structural characteristics, including its physically constrained form, and its fundamental power, timing, clock and signal integrity properties. With the STANDARD BLOCK architecture, quantization of the STANDARD BLOCKs' form dimensions relative to IC dimensions can be substantially constant and scalable with increased IC complexity. Thus, STANDARD BLOCK architecture can be applied to any IC designs as well as any intellectual property (IP) designs.

摘要翻译： 集成电路（IC）设计的STANDARD BLOCK架构。 STANDARD BLOCK架构提供了一个新的抽象级别，其粒度和规律性最适合于复杂的大规模深亚微米IC设计的物理实现。 为此，STANDARD BLOCK架构结合了基于标准单元和基于功能块的架构的优势。 STANDARD BLOCK架构包括一个物理约束的标准块形式，其具有一个固定或量化的尺寸和一个可变尺寸，其范围在预定义的限制之间。 标准块粒度大于标准单元粒度，使得每个标准块包括多个标准单元。 在STANDARD BLOCK架构中，每个STANDARD BLOCK具有灵活的物理设计特性。 在这种设计风格中，标准块被提供作为一般物理抽象，使得每个标准块类似于黑箱模型，其大部分内部设计方面对于顶级装配工具是不可见的，而选定的设计方面保持可见。 每个标准块的全球设计方面包括其基本的架构和结构特性，包括其物理约束形式及其基本功率，时序，时钟和信号完整性。 利用STANDARD BLOCK架构，相对于IC尺寸的标准块的尺寸的量化可以基本上恒定并且随着IC复杂性的增加而可扩展。 因此，STANDARD BLOCK架构可以应用于任何IC设计以及任何知识产权（IP）设计。

公开(公告)号：US06467074B1

公开(公告)日：2002-10-15

申请号：US09532330

申请日：2000-03-21

申请人： Athanassios Katsioulas ,  Stan Chow ,  Jacob Avidan ,  Dimitris Fotakis

发明人： Athanassios Katsioulas ,  Stan Chow ,  Jacob Avidan ,  Dimitris Fotakis

IPC分类号： G06F1750

CPC分类号： G06F15/7867 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/118

摘要： An integrated circuit (IC) architecture with STANDARD BLOCKs. The IC architecture forms a layout that includes a plurality of STANDARD BLOCKs, top-level cells, and hard IP blocks. The STANDARD BLOCKS form row-based or column-based STANDARD BLOCK ARRAY configurations in which STANDARD BLOCKs are placed adjacent to each other in a row or column configuration with their fixed or quantized dimension aligned and oriented perpendicular to the STANDARD BLOCK ARRAY direction. Individual STANDARD BLOCK ARRAYs can be spaced apart forming channels between them to allow for routing interconnections, or overlapping one another in a flipped configuration sharing VDD or GND power rails. The IC layout includes sites reserved for top-level cells that are placed in channels between STANDARD BLOCK ARRAYs, around the perimeter of STANDARD BLOCKs, or arranged in a staggered or diagonal configuration inside the STANDARD BLOCKs. The layout of the IC further includes power grid and clock grid structures providing, respectively, power and ground and clock distribution. Each of the STANDARD BLOCKs has a form that is physically constrained such that its dimensions feature one fixed or quantized dimension, and one variable dimension that ranges between predefined limits; a granularity larger than a standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells; and flexible physical design properties.

摘要翻译： 具有标准块的集成电路（IC）架构。 IC架构形成包括多个标准块，顶级单元和硬IP块的布局。 标准块形成基于行或列的STANDARD BLOCK ARRAY配置，其中STANDARD BLOCK以行或列配置彼此相邻放置，其固定或量化尺寸对准并垂直于STANDARD BLOCK ARRAY方向取向。 单个标准块阵列可以间隔开它们之间的通道，以允许路由互连，或者在共享VDD或GND电源轨的翻转配置中彼此重叠。 IC布局包括为顶级单元格保留的位置，放置在标准块阵列之间的通道中，围绕标准块的周边，或者以标准块内的交错或对角线配置布置。 IC的布局还包括分别提供电源和地和时钟分配的电网和时钟网格结构。 每个标准块具有物理约束的形式，使得其尺寸具有一个固定或量化尺寸，并且一个可变尺寸范围在预定义的限度之间; 大于标准单元粒度的粒度，使得每个标准块包括多个标准单元; 灵活的物理设计属性。

公开(公告)号：US20070245281A1

公开(公告)日：2007-10-18

申请号：US11734757

申请日：2007-04-12

申请人： Michael Riepe ,  Niranjana Balasundaram ,  Menno Verbeek ,  Hong Cai ,  Roger Carpenter ,  Jacob Avidan

发明人： Michael Riepe ,  Niranjana Balasundaram ,  Menno Verbeek ,  Hong Cai ,  Roger Carpenter ,  Jacob Avidan

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072

摘要： A method and system for performing placement-driven physical hierarchy generation in the context of an integrated circuit layout generation system is provided. This generation optimizes the physical hierarchy to improve placement of the cells in the layout, and the associated interconnect routability and delay. A new pre-clustering phase is introduced to maintain as much of the input logical hierarchy as possible while maintaining physical hierarchy quality. And a new cost function is described which is based on measuring the mutual affinity of cells in a virtually-flat placement. The new cost function is used during the new pre-clustering phase, as well as the common clustering, partitioning, and declustering/refinement phases of physical hierarchy generation.

摘要翻译： 提供了一种用于在集成电路布局生成系统的上下文中执行布置驱动物理层次生成的方法和系统。 这一代优化了物理层次结构，以改善布局中单元格的布局，以及相关联的互连可布线性和延迟。 引入了一个新的预聚类阶段，以保持尽可能多的输入逻辑层次结构，同时保持物理层次质量。 并且描述了新的成本函数，其基于测量细胞在几乎平坦的位置中的相互亲和力。 新的成本函数在新的聚类前阶段使用，以及物理层次生成的公共聚类，分割和分解/细化阶段。

公开(公告)号：US6158022A

公开(公告)日：2000-12-05

申请号：US59596

申请日：1998-04-13

申请人： Jacob Avidan

发明人： Jacob Avidan

IPC分类号： G06F17/50 ,  G06F13/00 ,  G01R31/28 ,  G06F11/00

CPC分类号： G06F17/5031

摘要： A circuit analyzer, adapted to run in the memory of a processing system, for characterizing the performance of a circuit under test. The circuit analyzer of the present invention obviates traditional design steps by using gray and transparent circuit elements in addition to the traditional black circuit elements.

摘要翻译： 一种电路分析器，适于在处理系统的存储器中运行，用于表征被测电路的性能。 本发明的电路分析器除了传统的黑电路元件之外，通过使用灰色和透明电路元件来避免传统的设计步骤。

公开(公告)号：US5740347A

公开(公告)日：1998-04-14

申请号：US429430

申请日：1995-05-01

申请人： Jacob Avidan

发明人： Jacob Avidan

IPC分类号： G06F17/50 ,  G06F13/00

CPC分类号： G06F17/5031

摘要： A method, apparatus and medium containing a computer program for analyzing timing in circuits. In one embodiment, the invention sets the direction of elements of a circuit by partitioning the circuit to identify a subcircuit including a pullup or pulldown block, then modeling the subcircuit as a single transistor, then setting the direction of that single transistor and then propagating the direction of that single transistor to other elements of the subcircuit. In another embodiment, the invention generates a gray box model by searching paths from a primary clock input of a circuit, determining worst and best paths among the multiple elements of the circuit and incorporating the best and worst path information in the gray box model. In another embodiment, the invention instantiates such a gray box model in a second circuit and performs timing checks on this second circuit.

摘要翻译： 一种包含用于分析电路中的定时的计算机程序的方法，装置和介质。 在一个实施例中，本发明通过划分电路来确定电路的元件的方向，以识别包括上拉或下拉块的分支电路，然后将子电路建模为单个晶体管，然后设置该单个晶体管的方向，然后传播 该单晶体管的方向到子电路的其他元件。 在另一个实施例中，本发明通过搜索来自电路的主时钟输入的路径来生成灰盒模型，确定电路的多个元件中的最差和最佳路径，并将最佳和最差路径信息并入灰盒模型中。 在另一个实施例中，本发明在第二电路中实例化这样的灰盒模型，并对该第二电路执行定时检查。

公开(公告)号：US08407650B1

公开(公告)日：2013-03-26

申请号：US12129916

申请日：2008-05-30

申请人： Jacob Avidan ,  Sandeep Grover ,  Roger Carpenter ,  Philippe Sarrazin

发明人： Jacob Avidan ,  Sandeep Grover ,  Roger Carpenter ,  Philippe Sarrazin

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.

摘要翻译： 在各种实施例中，重复块的每个可能的不同实例可以被同时修改用于芯片路由。 可以在重复块的所有实例相同或基本相同的情况下实现重复块。 可以基于对所有实例的I / O的分析来确定引脚放置。 针脚放置可以被生成为与所有实例相同或基本相似。 天桥拦截可以设计成重复的块，以使全局路由器能够穿过重复的块。 缓冲器和相关引脚可以插入飞越空间内的重复块，其中全局路由器通过区域引脚连接到所需的缓冲区。