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    Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers
    8.
    发明授权
    Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers 失效
    形成具有各向异性氧化的氮化物层的集成电路器件的方法

    公开(公告)号：US07989333B2

    公开(公告)日：2011-08-02

    申请号：US12468296

    申请日：2009-05-19

    申请人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    发明人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3105 ,  H01L29/6653

    摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。 然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。 氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

    Methods for fabricating improved gate dielectrics
    9.
    发明授权
    Methods for fabricating improved gate dielectrics 失效
    制造改进的栅极电介质的方法

    公开(公告)号：US07759263B2

    公开(公告)日：2010-07-20

    申请号：US11806338

    申请日：2007-05-31

    申请人： Woong-Hee Sohn ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Hee-Sook Park ,  Jae-Hwa Park ,  Geum-Jung Seong

    发明人： Woong-Hee Sohn ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Hee-Sook Park ,  Jae-Hwa Park ,  Geum-Jung Seong

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823481 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/981

    摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译： 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

    Semiconductor devices including high-k dielectric materials
    10.
    发明授权
    Semiconductor devices including high-k dielectric materials 失效
    包括高k电介质材料的半导体器件

    公开(公告)号：US07696552B2

    公开(公告)日：2010-04-13

    申请号：US11227541

    申请日：2005-09-15

    申请人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Byung-Hak Lee ,  Hee-Sook Park

    发明人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Byung-Hak Lee ,  Hee-Sook Park

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

    摘要： A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.

    摘要翻译： 半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，在电介质层上掺杂有P型杂质的多晶硅的第二导电层，以及第三导电层 层，其包括在第二导电层上的金属。 在一些器件中，第一栅极结构形成在主单元区域中，并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。 控制栅极包括掺杂有P型杂质和金属层的多晶硅层。 第二栅极结构形成在主单元区域的外部，并且包括隧道氧化物层，导电层和金属层。 第三栅极结构形成在周边单元区域中，并且包括具有比导电层窄的宽度的隧道氧化物，导电层和高k电介质层。 还公开了方法实施例。