公开(公告)号：US08184026B2

公开(公告)日：2012-05-22

申请号：US12894234

申请日：2010-09-30

申请人： Bo Sung Kim ,  Seung Nam Park ,  Jae Il Cheon

发明人： Bo Sung Kim ,  Seung Nam Park ,  Jae Il Cheon

IPC分类号： H03M9/00

CPC分类号： H04L25/14

摘要： An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block.

摘要翻译： 优化的移动工业处理器接口（MIPI）包括发射机物理层（PHY）层，被配置为将输入数据转换为串行数据并且与高速时钟同步地发送串行数据;接收器PHY层，被配置为将串行数据转换成 与从发射机接收的时钟同步的8位并行数据，配置为合并从接收机PHY层接收的并行数据的位合并块，以便使用多个通道形成32位数据并发送32位数据 接收器协议层被配置为解码并识别从位合并块接收到的数据。

公开(公告)号：US20110156936A1

公开(公告)日：2011-06-30

申请号：US12894234

申请日：2010-09-30

申请人： Bo-Sung Kim ,  Seung Nam Park ,  Jae Il Cheon

发明人： Bo-Sung Kim ,  Seung Nam Park ,  Jae Il Cheon

IPC分类号： H03M9/00

CPC分类号： H04L25/14

摘要： An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block.

摘要翻译： 优化的移动工业处理器接口（MIPI）包括发射机物理层（PHY）层，被配置为将输入数据转换为串行数据并且与高速时钟同步地发送串行数据;接收器PHY层，被配置为将串行数据转换成 与从发射机接收的时钟同步的8位并行数据，配置为合并从接收机PHY层接收的并行数据的位合并块，以便使用多个通道形成32位数据并发送32位数据 接收器协议层被配置为解码并识别从位合并块接收到的数据。