公开(公告)号：US08354671B1

公开(公告)日：2013-01-15

申请号：US12781627

申请日：2010-05-17

申请人： Hsung Jai Im ,  Henley Liu ,  Jae-Gyung Ahn ,  Tony Le ,  Patrick J. Crotty

发明人： Hsung Jai Im ,  Henley Liu ,  Jae-Gyung Ahn ,  Tony Le ,  Patrick J. Crotty

IPC分类号： H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  G01R31/26 ,  G01N27/00

CPC分类号： H01L22/34 ,  H01L29/42364

摘要： A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.

摘要翻译： 公开了一种在IC中设置Vgg的技术。 该技术包括指定IC的设计可靠性寿命，并建立足以实现设计可靠性寿命的IC的最大栅极偏置和栅极电介质厚度之间的关系。 制造IC并测量栅介质厚度。 根据栅极介电厚度和最大栅极偏置与栅极介质厚度之间的关系确定最大栅极偏置电压，并且设置IC的Vgg微调电路以提供具有最大栅极偏置电压的Vgg，其将实现设计可靠性 根据测量的栅极介电厚度的寿命。

公开(公告)号：US08350253B1

公开(公告)日：2013-01-08

申请号：US12697027

申请日：2010-01-29

申请人： Bei Zhu ,  Hong-Tze Pan ,  Bang-Thu Nguyen ,  Qi Lin ,  Zhiyuan Wu ,  Ping-Chin Yeh ,  Jae-Gyung Ahn ,  Yun Wu

发明人： Bei Zhu ,  Hong-Tze Pan ,  Bang-Thu Nguyen ,  Qi Lin ,  Zhiyuan Wu ,  Ping-Chin Yeh ,  Jae-Gyung Ahn ,  Yun Wu

IPC分类号： H01L29/06

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7848

摘要： An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

摘要翻译： 在半导体衬底上制造的集成电路（IC）具有形成在半导体衬底中的沟道区上的有源栅极结构。 在绝缘隔离结构上形成虚拟栅极结构。 虚拟栅极结构和有源栅极结构具有相同的宽度。 虚拟栅极结构上的侧壁间隔物覆盖在应变诱导插入件和介电隔离结构之间的半导体部分。

公开(公告)号：US20120229203A1

公开(公告)日：2012-09-13

申请号：US13042122

申请日：2011-03-07

申请人： Sharmin Sadoughi ,  Jae-Gyung Ahn

发明人： Sharmin Sadoughi ,  Jae-Gyung Ahn

IPC分类号： H03H2/00

CPC分类号： H03K17/18 ,  H01L22/22 ,  H01L2924/0002 ,  H03K17/12 ,  H01L2924/00

摘要： A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.

摘要翻译： 可以根据性能对多指装置进行校准。 多指装置可以包括被配置为保持活动的第一手指和最初与第一手指同时激活的第二手指有效。 可以确定IC内的多指装置的劣化度量。 降解的量度可以与降解阈值进行比较。 响应于确定降解度量达到降解阈值，可以激活多指装置的手指。

公开(公告)号：US07419748B1

公开(公告)日：2008-09-02

申请号：US10925606

申请日：2004-08-24

申请人： Jae-Gyung Ahn

发明人： Jae-Gyung Ahn

IPC分类号： G03F1/00

CPC分类号： G03F7/70433 ,  G03F1/40

摘要： A photomask and a method for forming a photomask are disclosed in which the photomask pattern is modified to bridge features that are likely to produce electrostatic discharge related defects. In one embodiment those adjacent features that are closely spaced together and have a high surface area differential, are bridged using a bridge that has a width less than the minimum optical resolution of the photolithography process.

摘要翻译： 公开了光掩模和形成光掩模的方法，其中光掩模图案被修改以桥接可能产生静电放电相关缺陷的特征。 在一个实施例中，使用具有小于光刻工艺的最小光学分辨率的宽度的桥桥接紧密间隔在一起且具有高表面积差的相邻特征。

公开(公告)号：US5877532A

公开(公告)日：1999-03-02

申请号：US853505

申请日：1997-05-08

申请人： Jae-Gyung Ahn ,  Jeong-Hwan Son

发明人： Jae-Gyung Ahn ,  Jeong-Hwan Son

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/0847

摘要： A trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by the respective etching-back processes. Using the gate as a mask, a low concentration region for the LDD structure is formed. Using the gate and sidewall as a mask, a source region and a drain region are formed. Thus, the channel region makes a right angle with the trench or recess, and the channel region is bent. Further, the channel region is made to be formed so as to be longer than the width of the gate. Since the low concentration region for the LDD structure is formed only in the drain region, the source resistance can be decreased, and a gate with a narrow width can be easily formed. Further, even if the channel length is short, the occurrence of the DIBL phenomenon can be suppressed.

摘要翻译： 沟槽或凹槽形成在半导体衬底的预定部分中。 然后，在沟槽或凹槽的一侧，通过相应的回蚀工艺形成具有侧壁的栅极。 使用栅极作为掩模，形成LDD结构的低浓度区域。 使用栅极和侧壁作为掩模，形成源区和漏区。 因此，通道区域与沟槽或凹部成直角，沟道区域弯曲。 此外，使沟道区域形成为比栅极的宽度长。 由于LDD结构的低浓度区域仅形成在漏极区域中，所以可以降低源极电阻，并且可以容易地形成宽度窄的栅极。 此外，即使通道长度短，也可以抑制DIBL现象的发生。

公开(公告)号：US07956385B1

公开(公告)日：2011-06-07

申请号：US12847957

申请日：2010-07-30

申请人： Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak K. Nayak ,  Daniel Gitlin

发明人： Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak K. Nayak ,  Daniel Gitlin

IPC分类号： H01L23/525

CPC分类号： H01L27/0251

摘要： A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

摘要翻译： 公开了一种用于在制造集成电路器件期间保护晶体管的电路。 该电路包括晶体管，其晶体管具有形成在集成电路器件的管芯中的有源区上的栅极; 形成在集成电路器件的管芯中的保护元件; 以及耦合在所述晶体管的栅极和所述保护元件之间的可编程互连，所述可编程互连使得所述保护元件能够与所述晶体管分离。

公开(公告)号：US06518135B1

公开(公告)日：2003-02-11

申请号：US09961484

申请日：2001-09-24

申请人： Jae-Gyung Ahn

发明人： Jae-Gyung Ahn

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/41783

摘要： A method for forming a localized halo implant region, comprises: implanting a first dosage of ions of a first type toward a surface of a substrate having a gate electrode formed thereon, so as to form a lightly doped region adjacent to the gate electrode; forming a disposable spacer on a sidewall of the gate electrode; forming an elevated source/drain structure adjacent to the disposable spacer; implanting a second dosage of ions of the first type toward the surface of the substrate so as to form a heavily doped region adjacent to the disposable spacer; removing the disposable spacer; and tilt-angle implanting at least one dosage of ions of a second type toward a gap created by the disposable spacer having been removed so as to form a localized halo implant region in the substrate, preferably by utilizing shadow effects of the gate electrode and the elevated source/drain structure.

摘要翻译： 一种用于形成局部晕圈注入区域的方法，包括：将第一类型离子的第一剂量注入到其上形成有栅电极的衬底的表面上，以形成与栅电极相邻的轻掺杂区域; 在所述栅电极的侧壁上形成一次性间隔件; 形成与所述一次性间隔件相邻的升高的源极/漏极结构; 将第一类型的离子的第二剂量植入衬底的表面，以便形成与一次性衬垫相邻的重掺杂区域; 去除一次性间隔件; 并且倾斜角度将至少一次剂量的第二类型的离子注入由已被去除的一次性间隔物产生的间隙，以在衬底中形成局部的晕圈注入区域，优选地通过利用栅电极和 源/排水结构较高。

公开(公告)号：US5953616A

公开(公告)日：1999-09-14

申请号：US74595

申请日：1998-05-08

申请人： Jae Gyung Ahn

发明人： Jae Gyung Ahn

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L29/6659

摘要： A method of fabricating an MOS device that includes self-aligned suicides, the method including two amorphization implantations, both of which follow formation of the self-aligned source/drain regions of the device but precede formation of the self-aligned suicides. The first consists of implantation of low-energy heavy ions, preferably of energies 15-20 keV, while the second consists of implantation of more energetic heavy ions, preferably of energies at least 40 keV.

摘要翻译： 一种制造包括自对准自杀的MOS器件的方法，所述方法包括两个非晶化注入，两者都遵循器件的自对准源极/漏极区的形成，但在形成自对准自杀之前。 第一种方法是将低能量重离子注入，优选能量为15-20keV，而第二种是注入更多能量较重的离子，优选能量至少为40keV。

公开(公告)号：US08653844B2

公开(公告)日：2014-02-18

申请号：US13042122

申请日：2011-03-07

申请人： Sharmin Sadoughi ,  Jae-Gyung Ahn

发明人： Sharmin Sadoughi ,  Jae-Gyung Ahn

IPC分类号： G01R31/3187

CPC分类号： H03K17/18 ,  H01L22/22 ,  H01L2924/0002 ,  H03K17/12 ,  H01L2924/00

摘要： A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.

摘要翻译： 可以根据性能对多指装置进行校准。 多指装置可以包括被配置为保持活动的第一手指和最初与第一手指同时激活的第二手指有效。 可以确定IC内的多指装置的劣化度量。 降解的量度可以与降解阈值进行比较。 响应于确定降解度量达到降解阈值，可以激活多指装置的手指。

公开(公告)号：US08329568B1

公开(公告)日：2012-12-11

申请号：US12772969

申请日：2010-05-03

申请人： Jae-Gyung Ahn ,  Myongseob Kim ,  Ping-Chin Yeh ,  Zhiyuan Wu ,  John Cooksey

发明人： Jae-Gyung Ahn ,  Myongseob Kim ,  Ping-Chin Yeh ,  Zhiyuan Wu ,  John Cooksey

IPC分类号： H01L21/425

CPC分类号： H01L29/665 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.

摘要翻译： 在本发明的一个实施例中，提供了场效应晶体管器件。 场效应晶体管器件包括有源区，包括第一导电类型的第一半导体材料。 通道区域包括在有效区域内。 栅极区域覆盖沟道区域，并且第一源极/漏极区域和第二源极/漏极区域被嵌入有源区域中并且被沟道区域彼此间隔开。 第一源极/漏极区域和第二源极/漏极区域各自包括与第一导电类型相反的第二导电类型的第二半导体材料。 阱区域嵌入有源区域中，并且通过沟道区域和第二源极/漏极区域与第一源极/漏极区域间隔开。 阱抽头区域包括第一导电类型的第二半导体材料。 第一源极/漏极区域和第二源极/漏极区域以及阱阱区域是外延沉积物。