公开(公告)号：US20090044063A1

公开(公告)日：2009-02-12

申请号：US11974342

申请日：2007-10-12

申请人： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

发明人： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/2602 ,  G11C2029/5602

摘要： A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

摘要翻译： 半导体存储器件包括存储器核心单元，N个数据输出缓冲器，N个数据输出端口以及多个测试逻辑电路。 存储核心单元通过N条数据线存储测试数据。 N个数据输出缓冲器分别连接到相应的N个数据线。 N个数据输出端口连接到相应的N个数据输出缓冲器，并分别与外部测试仪交换测试数据。 多个测试逻辑电路通过来自N条数据线的K条数据线接收测试数据，对所接收的测试数据进行测试逻辑运算，并提供一个数据输出缓冲器控制信号，该信号确定N个数据输出缓冲器的激活 测试模式下的数据输出缓冲区。 半导体存储器件降低了测试周期。

公开(公告)号：US06396756B1

公开(公告)日：2002-05-28

申请号：US09684190

申请日：2000-10-06

申请人： Sang-Seok Kang ,  Jae-Hoon Joo ,  Young-Ok Cho

发明人： Sang-Seok Kang ,  Jae-Hoon Joo ,  Young-Ok Cho

IPC分类号： G11C700

CPC分类号： G11C11/4096

摘要： Integrated circuit memory devices include first and second memory cell arrays, first and second transmission parts between the first and second memory cell arrays, and first and second input/output selection parts between the first and second memory cell arrays, wherein the first transmission part is adjacent the first input/output selection part and wherein the second transmission part is adjacent the second input/output selection part. A transistor in the first transmission part and a transistor in the first input/output selection part can share a first common source/drain region. A transistor in the second transmission part and a transistor in the second input/output selection part also can share a second common source/drain region. First and second input/output selection parts also may be provided between the first and second transmission parts. At least one sense amplifier part may be provided between the first and second input/output selection parts.

摘要翻译： 集成电路存储器件包括第一和第二存储单元阵列，第一和第二存储单元阵列之间的第一和第二传输部分以及第一和第二存储单元阵列之间的第一和第二输入/输出选择部分，其中第一传输部分 邻近第一输入/输出选择部分，并且其中第二传输部分与第二输入/输出选择部分相邻。 第一传输部分中的晶体管和第一输入/输出选择部分中的晶体管可以共享第一公共源极/漏极区域。 第二传输部分中的晶体管和第二输入/输出选择部分中的晶体管也可以共享第二公共源极/漏极区域。 也可以在第一和第二传动部件之间设置第一和第二输入/输出选择部件。 可以在第一和第二输入/输出选择部分之间提供至少一个读出放大器部分。

公开(公告)号：US08228736B2

公开(公告)日：2012-07-24

申请号：US12591976

申请日：2009-12-07

申请人： Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

发明人： Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

IPC分类号： G11C16/04

CPC分类号： G06F1/206 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

摘要： A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

摘要翻译： 移动片上系统（SoC）包括微处理器和被配置为控制第一存储器的刷新的第一存储器控制器。 温度传感器检测第一存储器中的温度。 当从温度传感器接收到的第一温度信息指示检测到的温度偏离预定温度范围时，第一存储器控制器控制第一存储器以便不进行自刷新。 当从温度传感器接收到的第二温度信息指示检测到的温度处于预定温度范围时，第一存储器控制器向第一存储器输出自刷新命令。

公开(公告)号：US06345011B2

公开(公告)日：2002-02-05

申请号：US09758526

申请日：2001-01-10

申请人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

发明人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

IPC分类号： G11C800

CPC分类号： G11C7/10

摘要： A semiconductor memory device including a plurality of memory blocks having associated with one or more circuit blocks therearound, and a plurality of input/output lines associated with the memory blocks, is disclosed. The input/output lines are divided into at least a first group and a second group. First portions of the input/output lines of the first group are arranged between the adjacent memory blocks while first portions of the input/output lines of the second group are arranged within the circuit blocks around the adjacent memory blocks. Second portions of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second portions of the input/output lines of the second group are arranged between the adjacent memory blocks.

摘要翻译： 公开了一种包括与其周围的一个或多个电路块相关联的多个存储块的半导体存储器件，以及与存储器块相关联的多个输入/输出线。 输入/输出线分成至少第一组和第二组。 第一组的输入/输出线的第一部分被布置在相邻的存储块之间，而第二组的输入/输出线的第一部分被布置在邻近的存储块周围的电路块内。 第一组的输入/输出线的第二部分布置在存储块周围的电路块上，而第二组的输入/输出线的第二部分被布置在相邻的存储块之间。

公开(公告)号：US20110188334A1

公开(公告)日：2011-08-04

申请号：US13020450

申请日：2011-02-03

申请人： Sang-Seok KANG ,  Sang-Man BYUN ,  Jae-Hoon JOO

发明人： Sang-Seok KANG ,  Sang-Man BYUN ,  Jae-Hoon JOO

IPC分类号： G11C5/14 ,  H01H37/76

CPC分类号： G11C5/14 ,  H01H37/76

摘要： Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

摘要翻译： 提供了能够根据操作模式选择性地使用用于逻辑运算的电源电压的熔丝电路。 熔丝电路包括模式产生电路，电源电压选择电路和至少一个保险丝单元。 模式产生电路产生多个模式信号。 电源电压选择电路响应于多个模式信号选择多个电源电压中的一个，并将所选择的电源电压输出到第一节点。 每个熔丝单元耦合在第一节点和地电压之间，并且使用所选择的电源电压作为用于逻辑运算的电源电压。 因此，包括熔丝电路的半导体装置可以精确地测试熔丝的连接状态。

公开(公告)号：US07460428B2

公开(公告)日：2008-12-02

申请号：US11482141

申请日：2006-07-07

申请人： Jae-hoon Joo ,  Sang-seok Kang ,  Byung-heon Kwak ,  Kang-young Cho ,  Chang-hag Oh

发明人： Jae-hoon Joo ,  Sang-seok Kang ,  Byung-heon Kwak ,  Kang-young Cho ,  Chang-hag Oh

IPC分类号： G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/4087 ,  G11C2207/2227

摘要： Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.

摘要翻译： 提供了具有降低的电流消耗的DRAM和包括该DRAM的通信终端。 DRAM包括能够独立地供电的多个存储器组和用于选择性地使多个存储体中的一些存储器进入DPD模式的DPD控制器。

公开(公告)号：US20070008802A1

公开(公告)日：2007-01-11

申请号：US11482141

申请日：2006-07-07

申请人： Jae-hoon Joo ,  Sang-seok Kang ,  Byung-heon Kwak ,  Kang-young Cho ,  Chang-hag Oh

发明人： Jae-hoon Joo ,  Sang-seok Kang ,  Byung-heon Kwak ,  Kang-young Cho ,  Chang-hag Oh

IPC分类号： G11C5/14

CPC分类号： G11C11/4074 ,  G11C11/4087 ,  G11C2207/2227

摘要： Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.

摘要翻译： 提供了具有降低的电流消耗的DRAM和包括该DRAM的通信终端。 DRAM包括能够独立地供电的多个存储器组和用于选择性地使多个存储体中的一些存储器进入DPD模式的DPD控制器。

公开(公告)号：US06522597B2

公开(公告)日：2003-02-18

申请号：US09947392

申请日：2001-09-07

申请人： Jong Hyun Choi ,  Sang Seok Kang ,  Jae Hoon Joo

发明人： Jong Hyun Choi ,  Sang Seok Kang ,  Jae Hoon Joo

IPC分类号： G11C800

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

摘要： State change transition times of a semiconductor memory device is reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharging circuits and non-shared I/O lines which have only a single precharging circuit, effective contact resistance of the non-shared I/O lines are reduced by eliminating unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.

公开(公告)号：US06215723B1

公开(公告)日：2001-04-10

申请号：US09489236

申请日：2000-01-21

申请人： Sang-seok Kang ,  Jae-hoon Joo

发明人： Sang-seok Kang ,  Jae-hoon Joo

IPC分类号： G11C800

CPC分类号： G11C11/4087 ,  G11C8/04 ,  G11C8/10 ,  G11C11/4085

摘要： A semiconductor memory device for sequentially disabling activated word lines is provided. The semiconductor memory device having a plurality of word lines connected to a plurality of memory cells includes a predecoding unit for predecoding a row address received from the outside, a row decoding and word line driving block, which is connected to the predecoding unit and the plurality of word lines, for decoding an output of the predecoding unit, selecting some of the plurality of word lines, and activating the selected word lines and a controller connected to the predecoding unit and the row decoding and word line driving block, for receiving the row address, the output of the predecoding unit, and at least one control signal, generating at least one output signal, and sequentially disabling the activated word lines by enabling the at least one output signal in response to the row address and the output of the predecoding unit.

摘要翻译： 提供了用于顺序禁用激活字线的半导体存储器件。 具有连接到多个存储单元的多个字线的半导体存储器件包括预解码单元，用于对从外部接收的行地址进行预编码，行解码和字线驱动块，其连接到预解码单元和多个 的字线，用于解码预解码单元的输出，选择多个字线中的一些，并激活所选择的字线，以及连接到预解码单元和行解码和字线驱动块的控制器，用于接收行 地址，预解码单元的输出，以及至少一个控制信号，产生至少一个输出信号，以及通过响应于行地址和预解码的输出启用至少一个输出信号来顺序地禁用激活的字线 单元。

公开(公告)号：US08477553B2

公开(公告)日：2013-07-02

申请号：US13020450

申请日：2011-02-03

申请人： Sang-Seok Kang ,  Sang-Man Byun ,  Jae-Hoon Joo

发明人： Sang-Seok Kang ,  Sang-Man Byun ,  Jae-Hoon Joo

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  H01H37/76

摘要： Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

摘要翻译： 提供了能够根据操作模式选择性地使用用于逻辑运算的电源电压的熔丝电路。 熔丝电路包括模式产生电路，电源电压选择电路和至少一个保险丝单元。 模式产生电路产生多个模式信号。 电源电压选择电路响应于多个模式信号选择多个电源电压中的一个，并将所选择的电源电压输出到第一节点。 每个熔丝单元耦合在第一节点和地电压之间，并且使用所选择的电源电压作为用于逻辑运算的电源电压。 因此，包括熔丝电路的半导体装置可以精确地测试熔丝的连接状态。