公开(公告)号：US20180337193A1

公开(公告)日：2018-11-22

申请号：US16047712

申请日：2018-07-27

申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

公开(公告)号：US20160163730A1

公开(公告)日：2016-06-09

申请号：US14959209

申请日：2015-12-04

申请人： JOON-SUNG LIM ,  JANG-GN YUN ,  SUNGHOON BAE ,  JAESUN YUN ,  KYU-BAIK CHANG

发明人： JOON-SUNG LIM ,  JANG-GN YUN ,  SUNGHOON BAE ,  JAESUN YUN ,  KYU-BAIK CHANG

IPC分类号： H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.

摘要翻译： 半导体器件包括逻辑结构，该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体，逻辑结构上的存储器结构，插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构 以及连接结构，其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

公开(公告)号：US20160163635A1

公开(公告)日：2016-06-09

申请号：US14957113

申请日：2015-12-02

申请人： Jang-Gn Yun ,  Jaesun Yun ,  Joon-Sung Lim

发明人： Jang-Gn Yun ,  Jaesun Yun ,  Joon-Sung Lim

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/552 ,  H01L27/115

CPC分类号： H01L23/528 ,  H01L23/3192 ,  H01L23/552 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.

摘要翻译： 半导体器件包括设置在半导体衬底上的单元半导体图案。 在半导体衬底上设置半导体虚设图案。 半导体虚拟图案与单元半导体图案共面。 第一电路设置在半导体衬底和单元半导体图案之间。 第一互连结构设置在半导体衬底和单元半导体图案之间。 第一虚拟结构设置在半导体衬底和单元半导体图案之间。 第一虚拟结构的一部分与第一互连结构的一部分共面。 与半导体图案不重叠的第二虚拟结构设置在半导体衬底上。 第二虚拟结构的一部分与第一互连结构的一部分共面。 在电池半导体图案和半导体衬底之间以及第一电路和第一互连结构之上设置导电屏蔽图案。

公开(公告)号：US09728549B2

公开(公告)日：2017-08-08

申请号：US14974567

申请日：2015-12-18

申请人： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

发明人： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20150084204A1

公开(公告)日：2015-03-26

申请号：US14313031

申请日：2014-06-24

申请人： Jang-Gn Yun ,  Jaesun Yun ,  Hoosung Cho

发明人： Jang-Gn Yun ,  Jaesun Yun ,  Hoosung Cho

IPC分类号： H01L27/112 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76895 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of fabricating the same. The device may include a substrate including a cell array region and a peripheral circuit region, stacks on the cell array region of the substrate, the stacks having a first height and extending along a direction, a common source structure disposed between adjacent ones of the stacks, a peripheral logic structure disposed on the peripheral circuit region of the substrate and having a second height smaller than the first height, a plurality of upper interconnection lines disposed on the peripheral logic structure and extending parallel to each other, and a interconnection structure disposed between the peripheral logic structure and the upper interconnection lines, when viewed in vertical section, and electrically connected to at least two of the upper interconnection lines.

摘要翻译： 提供半导体器件及其制造方法。 该器件可以包括包括单元阵列区域和外围电路区域的衬底，堆叠在衬底的单元阵列区域上，堆叠具有第一高度并沿着方向延伸，布置在相邻堆叠之间的公共源结构 ，设置在所述基板的外围电路区域上并且具有小于所述第一高度的第二高度的外围逻辑结构，设置在所述外围逻辑结构上并且彼此平行延伸的多个上部互连线，以及布置在 周边逻辑结构和上互连线，当从垂直截面看时，并且电连接到至少两个上互连线。

公开(公告)号：US09741733B2

公开(公告)日：2017-08-22

申请号：US14962263

申请日：2015-12-08

申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

公开(公告)号：US20160163732A1

公开(公告)日：2016-06-09

申请号：US14962263

申请日：2015-12-08

申请人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

发明人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

摘要翻译： 提供了制造半导体器件的半导体器件和方法。 半导体器件可以包括在半导体衬底上包括开口的半导体图案。 外围晶体管和外围互连结构可以设置在半导体衬底和半导体图案之间。 外围互连结构可以电连接到外围晶体管。 单元栅极导电图案可以设置在半导体图案上。 单元垂直结构可以延伸穿过单元栅极导电图案并且可以连接到半导体图案。 单元位线接触插头可以设置在单元垂直结构上。 位线可以设置在单元位线接触插头上。 外围位线接触结构可以设置在位线和外围互连结构之间。 外围位线接触结构可延伸穿过半导体的开口。

公开(公告)号：US20170330894A1

公开(公告)日：2017-11-16

申请号：US15662714

申请日：2017-07-28

申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC分类号： H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

公开(公告)号：US10038009B2

公开(公告)日：2018-07-31

申请号：US15662714

申请日：2017-07-28

申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor.

公开(公告)号：US20170323901A1

公开(公告)日：2017-11-09

申请号：US15661718

申请日：2017-07-27

申请人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

发明人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.