公开(公告)号：US20120185820A1

公开(公告)日：2012-07-19

申请号：US13008901

申请日：2011-01-19

申请人： Suresh Kadiyala ,  Madhavi Kadiyala ,  Sanjay Banerjee ,  Satish Padmanabhan ,  James Player

发明人： Suresh Kadiyala ,  Madhavi Kadiyala ,  Sanjay Banerjee ,  Satish Padmanabhan ,  James Player

IPC分类号： G06F9/44

CPC分类号： G06F8/37

摘要： Systems and methods are disclosed to automatically generate software development tools for an automatically generated processor architecture by: receiving a description of a target processor; automatically generating a target compiler using a compiler generator; automatically generating a target assembler using an assembler generator; automatically generating a target linker using a linker generator; automatically generating a target simulator using a simulator generator; automatically generating a target profiler using a profiler generator; iteratively generating a new processor architecture by changing one or more parameters of the processor architecture until all user constraints or requirements are met using the generated target compiler, assembler, linker, simulator, and profiler; for each new processor architecture regenerating the target compiler, assembler, linker, simulator, profiler for the new processor architecture; and synthesizing an optimal generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，通过以下方式自动生成用于自动生成的处理器架构的软件开发工具：接收目标处理器的描述; 使用编译器生成器自动生成目标编译器; 使用汇编器生成器自动生成目标汇编程序; 使用链接器生成器自动生成目标链接器; 使用模拟器发生器自动生成目标模拟器; 使用分析器生成器自动生成目标分析器; 通过改变处理器架构的一个或多个参数来迭代地生成新的处理器架构，直到使用生成的目标编译器，汇编器，链接器，模拟器和分析器来满足所有用户约束或需求为止; 为每个新的处理器架构重新生成新的处理器架构的目标编译器，汇编器，链接器，模拟器，分析器; 以及将最佳生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US08336017B2

公开(公告)日：2012-12-18

申请号：US13008900

申请日：2011-01-19

申请人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

发明人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法以自动生成由计算机可读代码或模型描述的定制集成电路（IC）。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过以层次的方式改变架构的一个或多个参数来迭代地优化处理器架构，直到使用架构优化器（AO）满足表示为成本函数的所有定时和硬件约束; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20120185809A1

公开(公告)日：2012-07-19

申请号：US13008900

申请日：2011-01-19

申请人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

发明人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法以自动生成由计算机可读代码或模型描述的定制集成电路（IC）。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过以层次的方式改变架构的一个或多个参数来迭代地优化处理器架构，直到使用架构优化器（AO）满足表示为成本函数的所有定时和硬件约束; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。