REGULAR EXPRESSION SEARCHES UTILIZING GENERAL PURPOSE PROCESSORS ON A NETWORK INTERCONNECT
    1.
    发明申请
    REGULAR EXPRESSION SEARCHES UTILIZING GENERAL PURPOSE PROCESSORS ON A NETWORK INTERCONNECT 失效
    在网络互连中使用一般用途处理器的常规表达式搜索

    公开(公告)号:US20120221711A1

    公开(公告)日:2012-08-30

    申请号:US13036779

    申请日:2011-02-28

    IPC分类号: G06F15/16

    CPC分类号: H04L67/28

    摘要: A first hardware node in a network interconnect receives a data packet from a network. The first hardware node examines the data packet for a regular expression. In response to the first hardware node failing to identify the regular expression in the data packet, the data packet is forwarded to a second hardware node in the network interconnect for further examination of the data packet in order to search for the regular expression in the data packet.

    摘要翻译: 网络互连中的第一个硬件节点从网络接收数据包。 第一个硬件节点检查正则表达式的数据包。 响应于第一硬件节点未能识别数据分组中的正则表达式,数据分组被转发到网络互连中的第二硬件节点,以进一步检查数据分组,以便搜索数据中的正则表达式 包。

    DATA ENCRYPTION INTERFACE FOR REDUCING ENCRYPT LATENCY IMPACT ON STANDARD TRAFFIC
    3.
    发明申请
    DATA ENCRYPTION INTERFACE FOR REDUCING ENCRYPT LATENCY IMPACT ON STANDARD TRAFFIC 审中-公开
    数据加密接口减少加密对标准交通的影响

    公开(公告)号:US20090144564A1

    公开(公告)日:2009-06-04

    申请号:US12364610

    申请日:2009-02-03

    IPC分类号: H04L9/06

    CPC分类号: G06F21/72 H04L9/00

    摘要: Methods and apparatus that may be utilized in systems to reduce the impact of latency associated with encrypting data on non-encrypted data are provided. Secure and non-secure data may be routed independently. Thus, non-secure data may be forwarded on (e.g., to targeted write buffers), without waiting for previously sent secure data to be encrypted. As a result, non-secure data may be made available for subsequent processing much earlier than in conventional systems utilizing a common data path for both secure and non-secure data.

    摘要翻译: 提供了可以在系统中用于减少与未加密数据加密数据相关的延迟的影响的方法和装置。 安全和非安全数据可以独立路由。 因此,非安全数据可以被转发(例如,到目标写缓冲器),而不等待先前发送的安全数据被加密。 因此,与使用用于安全和非安全数据的公共数据路径的常规系统相比,非安全数据可能比后续处理可用。

    Method, System and Computer Program Product for Preventing Execution of Pirated Software
    4.
    发明申请
    Method, System and Computer Program Product for Preventing Execution of Pirated Software 失效
    方法,系统和计算机程序产品,用于防止盗版软件的执行

    公开(公告)号:US20090063868A1

    公开(公告)日:2009-03-05

    申请号:US11850098

    申请日:2007-09-05

    IPC分类号: G06F21/22 H04L9/00

    摘要: A method, system and computer program product for preventing execution of pirated software. A file is loaded on an end user's computer containing a binary image that is generated by removing one or more code bits from an executable code. A request is sent to a remote server to return a software key required for execution of the executable code from the binary image. The software key is downloaded to the end user's computer on which the binary image is loaded. One or more bits from the software key is inserted into the appropriate location of the binary image to regenerate the executable code. The executable code is enabled for execution on the end user's computer only following the embedding of the one or more bits.

    摘要翻译: 一种用于防止盗版软件执行的方法,系统和计算机程序产品。 文件被加载到最终用户的计算机上,该计算机包含通过从可执行代码中删除一个或多个代码位而生成的二进制映像。 向远程服务器发送请求,以从二进制映像返回执行可执行代码所需的软件密钥。 软件密钥被下载到加载了二进制图像的最终用户的计算机上。 来自软件密钥的一个或多个位被插入二进制图像的适当位置以重新生成可执行代码。 只有在嵌入一个或多个位之后,才能在最终用户的计算机上执行可执行代码。

    Combined cache inject and lock operation
    5.
    发明授权
    Combined cache inject and lock operation 有权
    组合缓存注入和锁定操作

    公开(公告)号:US09176885B2

    公开(公告)日:2015-11-03

    申请号:US13355613

    申请日:2012-01-23

    IPC分类号: G06F13/00 G06F12/08 G06F13/28

    CPC分类号: G06F12/0888 G06F13/28

    摘要: A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.

    摘要翻译: 电路装置和方法利用高速缓存注入逻辑来执行高速缓存注入和锁定操作,以将高速缓存行注入到高速缓冲存储器中,并且将高速缓存行与高速缓存行的通信并行地主动地锁定在高速缓存存储器中。 高速缓存注入逻辑可以另外限制可以存储在高速缓冲存储器中的锁定高速缓存行的最大数量,例如通过中止高速缓存注入和锁定操作,在不锁定的情况下注入高速缓存行,或者解锁和/或驱逐另一个高速缓存行 在缓存中。

    Preventing execution of pirated software
    6.
    发明授权
    Preventing execution of pirated software 失效
    防止盗版软件的执行

    公开(公告)号:US08385554B2

    公开(公告)日:2013-02-26

    申请号:US11850098

    申请日:2007-09-05

    IPC分类号: H04L29/06

    摘要: A method, system and computer program product for preventing execution of pirated software. A file is loaded on an end user's computer containing a binary image that is generated by removing one or more code bits from an executable code. A request is sent to a remote server to return a software key required for execution of the executable code from the binary image. The software key is downloaded to the end user's computer on which the binary image is loaded. One or more bits from the software key is inserted into the appropriate location of the binary image to regenerate the executable code. The executable code is enabled for execution on the end user's computer only following the embedding of the one or more bits.

    摘要翻译: 一种用于防止盗版软件执行的方法,系统和计算机程序产品。 文件被加载到最终用户的计算机上,该计算机包含通过从可执行代码中删除一个或多个代码位而生成的二进制映像。 向远程服务器发送请求,以从二进制映像返回执行可执行代码所需的软件密钥。 软件密钥被下载到加载了二进制图像的最终用户的计算机上。 来自软件密钥的一个或多个位被插入二进制图像的适当位置以重新生成可执行代码。 只有在嵌入一个或多个位之后,才能在最终用户的计算机上执行可执行代码。

    Pixel color accumulation in a ray tracing image processing system
    7.
    发明授权
    Pixel color accumulation in a ray tracing image processing system 有权
    光线跟踪图像处理系统中的像素颜色累积

    公开(公告)号:US07884819B2

    公开(公告)日:2011-02-08

    申请号:US11535581

    申请日:2006-09-27

    IPC分类号: G06T15/50

    CPC分类号: G06T15/50 G06T15/06

    摘要: By merging or adding the color contributions from objects intersected by secondary rays, the image processing system may accumulate color contributions to pixels from objects intersected by secondary rays as the further color contributions are determined. Furthermore, by associating a scaling factor of color contribution with objects and with secondary rays which intersect the objects, color contributions due to secondary ray/object intersections may be calculated at a later time than the color contribution to a pixel from original ray/object intersection. Consequently, it is not necessary for a vector throughput engine or a workload manager to wait for all secondary ray/object intersections to be determined before updating the color of a pixel.

    摘要翻译: 通过合并或添加由二次光线相交的物体的颜色贡献,图像处理系统可以累积对由二次光线相交的物体的像素的颜色贡献,因为确定了另外的颜色贡献。 此外,通过将颜色贡献的缩放因子与对象相交,并且与与对象相交的次要光线相关联,可以在比从原始光线/物体交叉点对像素的颜色贡献更晚的时间来计算由于次级光线/物体交叉点引起的颜色贡献 。 因此,在更新像素的颜色之前,矢量吞吐量引擎或工作负载管理器不必等待所有二次光线/物体交叉点的确定。

    Branch Prediction In A Computer Processor
    8.
    发明申请
    Branch Prediction In A Computer Processor 有权
    计算机处理器中的分支预测

    公开(公告)号:US20090271597A1

    公开(公告)日:2009-10-29

    申请号:US12108846

    申请日:2008-04-24

    IPC分类号: G06F9/38

    摘要: Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.

    摘要翻译: 公开了一种用于在计算机处理器中进行分支预测的方法,装置和产品,包括:在分支出现多于一次的算法中记录分支出现次序,每个分支的结果包括保持指针 到最近记录的结果的位置; 完成算法后,将指针复位到第一记录结果的位置; 并根据记录的结果预测分支的随后的分支结果。

    LOW-LATENCY DATA DECRYPTION INTERFACE
    9.
    发明申请
    LOW-LATENCY DATA DECRYPTION INTERFACE 有权
    低数据数据分解接口

    公开(公告)号:US20080288780A1

    公开(公告)日:2008-11-20

    申请号:US12142007

    申请日:2008-06-19

    IPC分类号: H04L9/00

    摘要: Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.

    摘要翻译: 提供了减少与解密加密数据相关的延迟的影响的方法和装置。 而不是等到整个加密数据包被验证(例如,通过检查数据传输错误),加密的数据可以在被接收时被流水线化到解密引擎,从而允许在验证之前开始解密。 在一些情况下,可以向解密引擎通知在验证过程期间检测到的数据传输错误,以防止报告错误的安全违规。

    METHOD AND SYSTEM FOR COHERENT DATA CORRECTNESS CHECKING USING A GLOBAL VISIBILITY AND PERSISTENT MEMORY MODEL
    10.
    发明申请
    METHOD AND SYSTEM FOR COHERENT DATA CORRECTNESS CHECKING USING A GLOBAL VISIBILITY AND PERSISTENT MEMORY MODEL 审中-公开
    使用全局可见性和持久记忆模型进行相关数据正确检查的方法和系统

    公开(公告)号:US20080010321A1

    公开(公告)日:2008-01-10

    申请号:US11425239

    申请日:2006-06-20

    IPC分类号: G06F17/30 G06F12/00

    CPC分类号: G06F12/0815 G06F2212/1032

    摘要: Exemplary embodiments include a system for coherent data correctness checking including: an address manager in operable communication with a processor, a DRAM model, and a IO bus; and a persistent memory model in operable communication with the processor, the IO bus, and a unit monitor checker, the persistent memory model operable for storing data information that can be compared with a data stored in an internal cache of the processor or the DRAM, wherein the unit monitor checker tracks memory operations throughout the system.

    摘要翻译: 示例性实施例包括用于相干数据正确性检查的系统,其包括:与处理器可操作地通信的地址管理器,DRAM模型和IO总线; 以及与处理器,IO总线和单元监视器检查器可操作地通信的持久存储器模型,持续存储器模型可操作用于存储可与存储在处理器或DRAM的内部高速缓存中的数据进行比较的数据信息, 其中单元监视器检查器跟踪整个系统中的存储器操作。