THIN FILM TRANSISTOR ARRAY PANEL
    2.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
    薄膜晶体管阵列

    公开(公告)号:US20100270555A1

    公开(公告)日:2010-10-28

    申请号:US12828669

    申请日:2010-07-01

    IPC分类号: H01L27/088 H01L29/786

    CPC分类号: G02F1/13624 G02F1/136286

    摘要: A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.

    摘要翻译: 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。

    Thin film transistor array panel
    3.
    发明授权
    Thin film transistor array panel 有权
    薄膜晶体管阵列面板

    公开(公告)号:US07777823B2

    公开(公告)日:2010-08-17

    申请号:US12018885

    申请日:2008-01-24

    IPC分类号: G02F1/1343

    CPC分类号: G02F1/13624 G02F1/136286

    摘要: A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.

    摘要翻译: 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。

    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管显示面板及其制造方法

    公开(公告)号:US20100148176A1

    公开(公告)日:2010-06-17

    申请号:US12480121

    申请日:2009-06-08

    IPC分类号: H01L29/04 H01L21/00

    摘要: The present invention relates to a thin film transistor array panel that includes an organic layer formed on a data line and a drain electrode disposed on a color filter. A thickness of a portion of the organic layer around a contact hole exposing a portion of the drain electrode is similar to a thickness of a portion of the organic layer around a contact hole exposing a portion of the data line. Having approximately the same thickness can prevent non-uniform etching of the organic layer around contact holes and deterioration of the thin film transistor array panel.

    摘要翻译: 本发明涉及一种薄膜晶体管阵列面板,其包括形成在数据线上的有机层和设置在滤色器上的漏电极。 暴露一部分漏电极的接触孔周围的有机层的一部分厚度类似于暴露一部分数据线的接触孔周围的有机层的一部分的厚度。 具有大致相同的厚度可以防止接触孔周围的有机层的不均匀蚀刻和薄膜晶体管阵列面板的劣化。

    TRANSPARENT DISPLAY APPARATUS
    5.
    发明申请
    TRANSPARENT DISPLAY APPARATUS 有权
    透明显示设备

    公开(公告)号:US20130162616A1

    公开(公告)日:2013-06-27

    申请号:US13462934

    申请日:2012-05-03

    IPC分类号: G09G5/00 G09G3/36

    摘要: A transparent display apparatus includes a display panel including a plurality of pixels arranged in rows and columns, a plurality of gate lines, a plurality of data lines including first and second data lines, a gate driver, and a data driver. Each of the pixels comprises sub-pixels arranged in a row direction, each gate line is operatively coupled to sub-pixels arranged in a corresponding row, and each first and second data line is operatively coupled to sub-pixels arranged in a corresponding column. The gate driver sequentially applies a gate signal to the pixels through the gate lines. The data driver applies sub-data signals to the sub-pixels through the first data lines, and applies down data signals to the sub-pixels through the second data lines. Each of the down data signals has a voltage level lower than a voltage level of a corresponding sub-data signal.

    摘要翻译: 透明显示装置包括:显示面板,包括排列成行和列的多个像素,多条栅极线,包括第一和第二数据线的多条数据线,栅极驱动器和数据驱动器。 每个像素包括沿行方向布置的子像素,每个栅极线可操作地耦合到布置在相应行中的子像素,并且每个第一和第二数据线可操作地耦合到布置在相应列中的子像素。 栅极驱动器通过栅极线顺序地对像素施加栅极信号。 数据驱动器通过第一数据线将子数据信号施加到子像素,并且通过第二数据线将数据信号施加到子像素。 每个下降数据信号具有低于相应子数据信号的电压电平的电压电平。

    ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
    阵列基板及其制造方法

    公开(公告)号:US20130087793A1

    公开(公告)日:2013-04-11

    申请号:US13553090

    申请日:2012-07-19

    IPC分类号: H01L33/08 H01L33/58

    摘要: An array substrate includes a base substrate and a contact part. The contact part is disposed on the base substrate. The contact part includes a first metal pattern, a disconnection control pattern and a connecting pattern. The second metal pattern is disposed on a layer different from the first metal pattern, the disconnection control pattern overlaps a side surface of the second metal pattern and a connecting pattern is formed on the first and second metal patterns and the disconnection control pattern and connects the first metal pattern with the second metal pattern.

    摘要翻译: 阵列基板包括基底基板和接触部件。 接触部分设置在基底基板上。 接触部分包括第一金属图案,断开控制图案和连接图案。 第二金属图案设置在与第一金属图案不同的层上,断开控制图案与第二金属图案的侧表面重叠,并且在第一和第二金属图案和断开控制图案上形成连接图案,并将 第一金属图案与第二金属图案。

    Thin film transistor display panel and manufacturing method thereof
    7.
    发明授权
    Thin film transistor display panel and manufacturing method thereof 有权
    薄膜晶体管显示面板及其制造方法

    公开(公告)号:US08035104B2

    公开(公告)日:2011-10-11

    申请号:US12480121

    申请日:2009-06-08

    IPC分类号: H01L29/04

    摘要: The present invention relates to a thin film transistor array panel that includes an organic layer formed on a data line and a drain electrode disposed on a color filter. A thickness of a portion of the organic layer around a contact hole exposing a portion of the drain electrode is similar to a thickness of a portion of the organic layer around a contact hole exposing a portion of the data line. Having approximately the same thickness can prevent non-uniform etching of the organic layer around contact holes and deterioration of the thin film transistor array panel.

    摘要翻译: 本发明涉及一种薄膜晶体管阵列面板,其包括形成在数据线上的有机层和设置在滤色器上的漏电极。 暴露一部分漏电极的接触孔周围的有机层的一部分厚度类似于暴露一部分数据线的接触孔周围的有机层的一部分的厚度。 具有大致相同的厚度可以防止接触孔周围的有机层的不均匀蚀刻和薄膜晶体管阵列面板的劣化。

    THIN FILM TRANSISTOR ARRAY PANEL
    8.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL 有权
    薄膜晶体管阵列

    公开(公告)号:US20080174712A1

    公开(公告)日:2008-07-24

    申请号:US12018885

    申请日:2008-01-24

    IPC分类号: G02F1/1368

    CPC分类号: G02F1/13624 G02F1/136286

    摘要: A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.

    摘要翻译: 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。