公开(公告)号：US08683558B2

公开(公告)日：2014-03-25

申请号：US13546341

申请日：2012-07-11

申请人： Jason A. Cox ,  Lydia M. Do

发明人： Jason A. Cox ,  Lydia M. Do

IPC分类号： H04L29/06

CPC分类号： H04L43/0876 ,  H04L63/102 ,  H04L67/22 ,  H04L67/38

摘要： An Activity Access Control (AAC) utility controls access to applications and devices by allowing an administrator to set terms of use/access regarding a applications and/or devices for a group of users, whose activity are monitored. The AAC utility also enables administrator and user access to a compromise facility via a centralized access point to establish or request changes to the terms of use/access. The AAC utility allows the administrator to dynamically update information and set terms based on real-time information collected during activity monitoring. Dynamic updates may also occur based on the monitored user's request, the priority of the requesting user(s), historical data, occurrence of a special event, completion of other internal or/external tasks, and/or pre-set limitations or thresholds. In addition, the AAC utility facilitates the real-time display or publishing of the terms of use, status information, and statistical information to users and the administrator.

摘要翻译： 活动访问控制（AAC）实用程序通过允许管理员为其活动被监视的一组用户设置关于应用和/或设备的使用/访问条款来控制对应用和设备的访问。 AAC实用程序还使管理员和用户能够通过集中式接入点访问妥协设施，以建立或请求对使用/访问条款的更改。 AAC实用程序允许管理员基于在活动监视期间收集的实时信息来动态地更新信息并设置术语。 动态更新还可以基于所监视的用户的请求，请求用户的优先级，历史数据，特殊事件的发生，其他内部或/外部任务的完成和/或预设的限制或阈值来进行。 此外，AAC实用程序有助于向用户和管理员实时显示或发布使用条款，状态信息和统计信息。

公开(公告)号：US08639889B2

公开(公告)日：2014-01-28

申请号：US13017250

申请日：2011-01-31

申请人： Jason A. Cox ,  Robert J. Dorsey ,  Kevin C K Lin ,  Eric F. Robinson

发明人： Jason A. Cox ,  Robert J. Dorsey ,  Kevin C K Lin ,  Eric F. Robinson

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0857 ,  Y02D10/13

摘要： One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.

摘要翻译： 一个实施例提供了一种缓存的存储器系统，其包括存储器高速缓存和被配置用于执行从处理器分派的读取和写入操作的多个读取权利要求（RC）机器。 根据提供有缓存的存储器系统的控制逻辑，在由第一和第二RC机器处理的第一和第二读或写操作之间检测到危险。 暂停第二个RC机器，并记录特定位位置的第二个操作的地址位的一个子集。 响应于第一操作完成，在特定位位置处的第一操作的地址位的子集被广播。 然后再次请求第二个操作。

公开(公告)号：US08352646B2

公开(公告)日：2013-01-08

申请号：US12969651

申请日：2010-12-16

申请人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

发明人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

IPC分类号： G06F13/28

CPC分类号： G06F12/084 ,  G06F12/0877 ,  Y02D10/13

摘要： Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

摘要翻译： 公开了用于直接访问高速缓冲存储器的方法和装置。 实施例包括由连接到用于高速缓存存储器的高速缓存控制器的直接访问管理器接收描述要对高速缓存存储器执行的区域范围零操作的区域范围零命令; 响应于接收到区域范围零命令，生成直接存储器访问区域范围零命令，直接存储器访问区域范围零命令具有操作代码和操作所在的高速缓冲存储器的物理地址的标识 执行 将直接存储器访问区范围零命令发送到高速缓存存储器的高速缓存控制器; 并且由缓存控制器根据操作代码和高速缓冲存储器的物理地址的识别来执行直接存储器访问区域范围零操作。

公开(公告)号：US20120198178A1

公开(公告)日：2012-08-02

申请号：US13017250

申请日：2011-01-31

申请人： Jason A. Cox ,  Robert J. Dorsey ,  Kevin CK Lin ,  Eric F. Robinson

发明人： Jason A. Cox ,  Robert J. Dorsey ,  Kevin CK Lin ,  Eric F. Robinson

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0857 ,  Y02D10/13

摘要： One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.

摘要翻译： 一个实施例提供了一种缓存的存储器系统，其包括存储器高速缓存和被配置用于执行从处理器分派的读取和写入操作的多个读取权利要求（RC）机器。 根据提供有缓存的存储器系统的控制逻辑，在由第一和第二RC机器处理的第一和第二读或写操作之间检测到危险。 暂停第二个RC机器，并记录特定位位置的第二个操作的地址位的一个子集。 响应于第一操作完成，在特定位位置处的第一操作的地址位的子集被广播。 然后再次请求第二个操作。

公开(公告)号：US20120127771A1

公开(公告)日：2012-05-24

申请号：US13364607

申请日：2012-02-02

申请人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

发明人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

IPC分类号： G11C15/04 ,  H01L21/8239

CPC分类号： H01L25/18 ,  G06F12/0895 ,  G06F12/1027 ,  G11C15/00 ,  G11C15/04 ,  H01L27/1203 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

摘要翻译： 提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。 本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。 这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。

公开(公告)号：US07752393B2

公开(公告)日：2010-07-06

申请号：US12114785

申请日：2008-05-04

申请人： Jason A. Cox ,  Kevin C. K. Lin ,  Eric F. Robinson

发明人： Jason A. Cox ,  Kevin C. K. Lin ,  Eric F. Robinson

IPC分类号： G06F12/00

CPC分类号： G06F9/3834 ,  G06F12/0802

摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.

摘要翻译： 提供了一种体现在用于设计，制造和/或测试用于将存储数据转发到流水线处理器中的负载的设计的机器可读存储介质中的设计结构。 在一个实现中，提供了一种处理器，其包括可解码指令的解码器和可操作以分别从解码器执行解码指令的多个执行单元。 多个执行单元包括可执行解码的加载指令和解码的存储指令并产生相应的加载存储器操作并存储存储器操作的加载/存储执行单元。 存储队列可操作以在一个或多个存储器操作完成之前缓冲一个或多个存储存储器操作，并且存储队列可操作以将缓存在存储队列中的一个或多个存储存储器操作的数据转发到负载 以逐个字节为基础的存储器操作。

公开(公告)号：US07689870B2

公开(公告)日：2010-03-30

申请号：US11561010

申请日：2006-11-17

申请人： Jason A. Cox ,  Keith A. DeWeese ,  Robert J. Dorsey ,  Eric F. Robinson ,  Thuong Q. Truong ,  Mark J. Wolski

发明人： Jason A. Cox ,  Keith A. DeWeese ,  Robert J. Dorsey ,  Eric F. Robinson ,  Thuong Q. Truong ,  Mark J. Wolski

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.

摘要翻译： 一种用于从非并发事件创建跟踪触发的方法和系统，所述系统包括：跟踪触发机制，包括：多个多路复用器，用于将多个信号分解成多组信号; 用于匹配多个信号以形成多个事件的模式匹配机制，以及跟踪阵列触发控制块，以对多个独立控制的事件执行一个或多个功能，以便从非并发事件创建灵活的跟踪触发控制 以控制诸如用于捕获跟踪数据的数据收集功能的启动和停止。

公开(公告)号：US08938588B2

公开(公告)日：2015-01-20

申请号：US12969617

申请日：2010-12-16

申请人： Jason A. Cox ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0833 ,  G06F12/084

摘要： Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is available and if the snoop machine is set to a reservation state; if the snoop machine is available and the snoop machine is in the reservation state, determining whether the instruction to execute the token-required cache operation owns a token or is a joint instruction; if the instruction is a joint instruction, instructing the operation to retry; if the instruction to execute the token-required cache operation owns a token, dispatching a cache controller; determining whether all required cache controllers of relevant compute nodes are available to execute the instruction; executing the instruction if the required cache controllers are available otherwise not executing the instruction.

摘要翻译： 确保共享缓存中令牌所需的高速缓存操作的进展，包括：侦听执行令牌所需缓存操作的指令; 确定窥探机是否可用，并且窥探机被设置为预约状态; 如果窥探机可用并且窥探机器处于预约状态，则确定执行令牌所需高速缓存操作的指令是否拥有令牌或是联合指令; 如果指令是联合指令，指示操作重试; 如果执行令牌需要的缓存操作的指令拥有一个令牌，则调度一个缓存控制器; 确定相关计算节点的所有需要​​的高速缓存控制器是否可用于执行指令; 如果所需的高速缓存控制器可用，则执行指令，否则不执行指令。

公开(公告)号：US08576599B2

公开(公告)日：2013-11-05

申请号：US13364607

申请日：2012-02-02

申请人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

发明人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

IPC分类号： G11C15/00 ,  G11C5/14

CPC分类号： H01L25/18 ,  G06F12/0895 ,  G06F12/1027 ,  G11C15/00 ,  G11C15/04 ,  H01L27/1203 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

摘要翻译： 提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。 本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。 这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。

公开(公告)号：US20120159640A1

公开(公告)日：2012-06-21

申请号：US12969634

申请日：2010-12-16

申请人： Jason A. Cox ,  Kevin C. Lin ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Kevin C. Lin ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F21/24

CPC分类号： G06F21/335

摘要： Acquiring access to a token controlled system resource, including: receiving, by a token broker, a command that requires access to the token controlled system resource, where the token broker is automated computing machinery for acquiring tokens and distributing the command to the token controlled system resource for execution; identifying, by the token broker, a first need state, the first need state indicating that the token broker requires access to the token controlled system resource to which the token broker does not possess a token; requesting, by the token broker, a configurable number of tokens to gain access to the token controlled system resource, without dispatching an operation handler for executing the command until at least one token is acquired; assigning, by the token broker, an acquired token to the operation handler; and dispatching, by the token broker, the operation handler and its assigned token for executing the command.

摘要翻译： 获取对令牌控制的系统资源的访问，包括：由令牌代理接收需要访问令牌控制的系统资源的命令，其中令牌代理是用于获取令牌的自动计算机器，并将命令分发给令牌控制系统 执行资源 由所述令牌代理识别第一需求状态，所述第一需求状态指示所述令牌代理需要访问所述令牌经纪人不具有令牌的令牌受控系统资源; 由令牌代理请求可配置数量的令牌以获得对令牌控制的系统资源的访问，而不调度用于执行该命令的操作处理器，直到获取至少一个令牌; 由令牌代理将所获取的令牌分配给操作处理程序; 并由令牌代理分派操作处理程序及其分配的用于执行命令的令牌。