公开(公告)号：US6127858A

公开(公告)日：2000-10-03

申请号：US71375

申请日：1998-04-30

Applicant: Jason C. Stinson ,  Edwin R. Lilya ,  Mathew B. Nazareth

Inventor： Jason C. Stinson ,  Edwin R. Lilya ,  Mathew B. Nazareth

IPC: G06F1/08 ,  H03K5/13 ,  H03L7/06 ,  H03K17/00 ,  H03H11/26

CPC classification number: G06F1/08 ,  H03K5/131 ,  H03K5/133 ,  H03L7/06

Abstract: A circuit to vary a frequency of an input clock is disclosed. The circuit includes a delay generator to generate at least two delayed clocks from the input clock and a select circuit coupled to receive the at least two delayed clocks and provide an output clock from one of the at least two delayed clocks. The select circuit switches the output clock from the one of the at least two delayed clocks to the other of the at least two delayed clocks on a first edge.

Abstract translation: 公开了改变输入时钟频率的电路。 该电路包括延迟发生器，以从输入时钟产生至少两个延迟的时钟;以及选择电路，其耦合以接收所述至少两个延迟的时钟，并从所述至少两个延迟的时钟之一提供输出时钟。 选择电路将输出时钟从至少两个延迟时钟中的一个切换到第一边缘上的至少两个延迟时钟中的另一个。

公开(公告)号：US06553545B1

公开(公告)日：2003-04-22

申请号：US09606484

申请日：2000-06-29

Applicant: Jason C. Stinson ,  Erik A. De La Iglesia

Inventor： Jason C. Stinson ,  Erik A. De La Iglesia

IPC: G06F1750

CPC classification number: H01L22/34 ,  G11C2029/0403 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus includes a test circuit, a first counter and a second counter. The test circuit is fabricated on a semiconductor substrate to generate an oscillating signal. The oscillating signal has a frequency that is dependent on at least in part a parameter of a process used to fabricate the test circuit. The first counter measures a time interval, and the second counter is coupled to the first counter to count a number of periods of the oscillating signal during the time interval.

Abstract translation: 一种装置包括测试电路，第一计数器和第二计数器。 测试电路制造在半导体衬底上以产生振荡信号。 振荡信号具有至少部分地取决于用于制造测试电路的过程的参数的频率。 第一计数器测量时间间隔，并且第二计数器耦合到第一计数器以在时间间隔期间对振荡信号的数个周期进行计数。

公开(公告)号：US5517136A

公开(公告)日：1996-05-14

申请号：US398123

申请日：1995-03-03

Applicant: David Harris ,  Sunny C. Huang ,  James Nadir ,  Ching-Hua Chu ,  Jason C. Stinson ,  Alper Ilkbahar

Inventor： David Harris ,  Sunny C. Huang ,  James Nadir ,  Ching-Hua Chu ,  Jason C. Stinson ,  Alper Ilkbahar

IPC: H03K19/017 ,  H03K19/096

CPC classification number: H03K19/01728 ,  H03K19/0963

Abstract: An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal. Odd-numbered half-cycles begin with a domino gate of the second type controlled by the second clock signal, followed by domino gates of the first type controlled by the fourth clock signal.

Abstract translation: 机会时间借用多米诺骨牌包括具有串联耦合并由第一，第二，第三和第四时钟信号控制的多个逻辑门的多米诺河流管线。 半周期中的第一个多米诺骨门由第一或第二时钟信号计时，其中半周期中最后的多米诺门由第三或第四个时钟周期计时。 第二时钟信号是第一时钟信号的倒数，并且第三和第四时钟信号具有本地延迟的时钟相位，其中第三和第四时钟信号的下降沿相对于相应的第一和第二时钟信号的下降沿被延迟 时钟信号。 在第一个半周期中，第一种类型的多米诺式门由第一时钟信号控制，同一类型的后续多米诺式门由第三时钟信号控制。 奇数半周期以由第二时钟信号控制的第二类型的多米诺门开始，其后是由第四时钟信号控制的第一类型的多米诺门。