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    Testable electronic circuit
    2.
    发明授权
    Testable electronic circuit 失效
    可测电子线路

    公开(公告)号：US07899641B2

    公开(公告)日：2011-03-01

    申请号：US11815313

    申请日：2006-01-31

    申请人： Hervé Fleury ,  Jean-Marc Yannou

    发明人： Hervé Fleury ,  Jean-Marc Yannou

    IPC分类号： G01R31/00

    CPC分类号： G01R31/318552 ,  G01R31/31727

    摘要： An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). The test control circuit (16) is coupled to control the clock multiplexing circuit (15a-c, 18) dependent on the mode assumed by the test control circuit (16). The clock multiplexing circuit (15a-c, 18) is arranged to substitute clock signals from respective ones of the data terminals (11a-c) temporarily at the clock inputs of respective ones of the groups (12a-c) in the test normal mode.

    摘要翻译： 电子电路包括耦合到电路的数据端子（11a-c）和功能电路（10）的触发器组（12a-c）。 每组（12a-c）都有一个时钟输入，用于对该组的触发器进行计时。 每个组（12a-c）可以在移位配置和功能配置之间切换，用于从数据终端串行地移动测试数据，并且并行地向功能电路（10）提供信号和/或从功能电路 功能电路（10）。 测试控制电路（16）可以在功能模式，测试移位模式和测试正常模式之间切换。 测试控制电路（16）耦合到触发器组（12a-c），以将功能模式中的功能配置和测试移位模式中的移位配置切换到功能模式。 时钟多路复用电路（15a-c，18）具有耦合到数据终端（11a-c）的输入和耦合到组（12a-c）的时钟输入的输出。 测试控制电路（16）被耦合以根据由测试控制电路（16）假设的模式来控制时钟复用电路（15a-c，18）。 时钟多路复用电路（15a-c，18）被配置为在测试正常模式下，在各个组（12a-c）的时钟输入端临时替代来自数据终端（11a-c）中的相应数据终端的时钟信号 。

    Integrated circuit with signature computation
    3.
    发明授权
    Integrated circuit with signature computation 有权
    具有签名计算的集成电路

    公开(公告)号：US07519494B2

    公开(公告)日：2009-04-14

    申请号：US10569721

    申请日：2004-08-26

    申请人： Stéphane Briere ,  Jean-Marc Yannou ,  Delphine Rivasseau

    发明人： Stéphane Briere ,  Jean-Marc Yannou ,  Delphine Rivasseau

    IPC分类号： G01R31/00

    CPC分类号： G01R31/318547 ,  H04N17/004 ,  H04N17/04

    摘要： The present invention relates to an integrated circuit (DEC V) for processing a plurality of data samples (P) of a data signal (I), wherein said integrated circuit is associated with a counter (CT) and comprises means (SIGN M) for computing a signature, said counter (CT) being adapted to trigger and stop a computation of a signature of said data signal (I), said signature being recalculated each time a data sample (P) of said data signal is output by said integrated circuit (DEC V). Use: Video decoder in a set-top-box.

    摘要翻译： 本发明涉及一种用于处理数据信号（I）的多个数据样本（P）的集成电路（DEC V），其中所述集成电路与计数器（CT）相关联，并且包括：装置（SIGN M），用于 计算签名，所述计数器（CT）适于触发和停止所述数据信号（I）的签名的计算，每当所述数据信号的数据样本（P）由所述集成电路输出时，所述签名被重新计算 （DEC V）。 使用：视频解码器在机顶盒中。

    Semiconductor device with improved ESD protection
    4.
    发明授权
    Semiconductor device with improved ESD protection 有权
    具有改进的ESD保护的半导体器件

    公开(公告)号：US08541865B2

    公开(公告)日：2013-09-24

    申请号：US12739333

    申请日：2008-10-22

    申请人： Jean-Marc Yannou ,  Johannes Van Zwol ,  Emmanuel Savin

    发明人： Jean-Marc Yannou ,  Johannes Van Zwol ,  Emmanuel Savin

    IPC分类号： H01L29/866 ,  H01L21/762

    CPC分类号： H01L23/60 ,  H01L23/481 ,  H01L25/167 ,  H01L27/0255 ,  H01L27/0814 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/3011 ,  H01L2924/00014

    摘要： The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.

    摘要翻译： 本发明涉及一种半导体器件，包括厚度小于100微米的半导体衬底（102），并具有第一衬底侧和相对的第二衬底侧。 多个至少四个具有小于20V的反向击穿电压的齐纳二极管或雪崩二极管（164,166,168,170）被限定在半导体衬底中并以串联方式彼此连接。 二极管限定在半导体衬底中的多个相互隔离的衬底岛（120,122,124,126）中，每个衬底岛至少有一个二极管。 衬底岛被从第一衬底侧延伸到第二衬底侧的贯穿衬底隔离件横向包围，并且包括将相应衬底岛与半导体衬底的相应横向周围区域电隔离的填充物（128）。

    SEMICONDUCTOR DEVICE WITH IMPROVED ESD PROTECTION
    5.
    发明申请
    SEMICONDUCTOR DEVICE WITH IMPROVED ESD PROTECTION 有权
    具有改进的ESD保护的半导体器件

    公开(公告)号：US20110121425A1

    公开(公告)日：2011-05-26

    申请号：US12739333

    申请日：2008-10-22

    申请人： Jean-Marc Yannou ,  Johannes Van Zwol ,  Emmanuel Savin

    发明人： Jean-Marc Yannou ,  Johannes Van Zwol ,  Emmanuel Savin

    IPC分类号： H01L29/866 ,  H01L21/762

    CPC分类号： H01L23/60 ,  H01L23/481 ,  H01L25/167 ,  H01L27/0255 ,  H01L27/0814 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/3011 ,  H01L2924/00014

    摘要： The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.

    摘要翻译： 本发明涉及一种半导体器件，包括厚度小于100微米的半导体衬底（102），并具有第一衬底侧和相对的第二衬底侧。 多个至少四个具有小于20V的反向击穿电压的齐纳二极管或雪崩二极管（164,166,168,170）被限定在半导体衬底中并以串联方式彼此连接。 二极管限定在半导体衬底中的多个相互隔离的衬底岛（120,122,124,126）中，每个衬底岛至少有一个二极管。 衬底岛被从第一衬底侧延伸到第二衬底侧的贯穿衬底隔离件横向包围，并且包括将相应衬底岛与半导体衬底的相应横向周围区域电隔离的填充物（128）。

    Electronic circuit comprising a secret sub-module
    10.
    发明授权
    Electronic circuit comprising a secret sub-module 有权
    电子电路包括秘密子模块

    公开(公告)号：US07519496B2

    公开(公告)日：2009-04-14

    申请号：US10571834

    申请日：2004-09-10

    申请人： Jean-Marc Yannou ,  Hervé Fleury ,  Hervé Vincent

    发明人： Jean-Marc Yannou ,  Hervé Fleury ,  Hervé Vincent

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318536 ,  G01R31/31719 ,  G01R31/318541 ,  G01R31/318555

    摘要： The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including a secret sub-module (4) for performing a function, scan chains; a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.

    摘要翻译： 本发明涉及一种包括连接到电路的其余部分的子模块组件（2）的电子电路，子模块组件包括用于执行功能的秘密子模块（4），扫描链; 包括用于向扫描链施加输入信号的模式发生器（5）的内置自检电路和用于检查来自扫描链的输出信号的签名寄存器（6）。 为了保持子模块的秘密，扫描链不连接到电路的其余部分。