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    Zero mask high density metal/insulator/metal capacitor
    4.
    发明授权
    Zero mask high density metal/insulator/metal capacitor 有权

    公开(公告)号：US06646323B2

    公开(公告)日：2003-11-11

    申请号：US09849730

    申请日：2001-05-04

    申请人： Christoph Dirnecker ,  Jeffrey A. Babcock ,  Michael Schober ,  Scott G. Balster ,  Angelo Pinto

    发明人： Christoph Dirnecker ,  Jeffrey A. Babcock ,  Michael Schober ,  Scott G. Balster ,  Angelo Pinto

    IPC分类号： H01L2900

    CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor. The resulting capacitor has a relatively large effective electrode surface area (which is a function of the depth of the via) for a given lateral dimension.

    Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
    7.
    发明授权
    Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures 有权
    肖特基结场效应晶体管（JFET）结构和形成JFET结构的方法

    公开(公告)号：US08207559B2

    公开(公告)日：2012-06-26

    申请号：US12498141

    申请日：2009-07-06

    申请人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

    发明人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

    IPC分类号： H01L29/66

    CPC分类号： H01L27/095 ,  H01L27/0207 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/808 ,  H01L29/812

    摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.

    摘要翻译： 根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。 结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。 此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。 根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接 场效应晶体管（JFET）。 在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。 根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。 该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。 掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。 此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。 这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。