公开(公告)号：US09058455B2

公开(公告)日：2015-06-16

申请号：US13354705

申请日：2012-01-20

Applicant: James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/48 ,  H03H9/64 ,  H01L23/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L25/16

CPC classification number: H01L41/293 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L25/16 ,  H01L27/0694 ,  H01L28/40 ,  H01L41/0815 ,  H01L41/25 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2225/06548 ,  H03H9/64

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract translation: 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

公开(公告)号：US08946013B2

公开(公告)日：2015-02-03

申请号：US13364663

申请日：2012-02-02

Applicant: Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

Inventor： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

IPC: H01L21/00 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Abstract translation: 形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。 因此，漏极区域与栅电极的边缘自对准。 一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。 在形成漏极区域之后，一次性结构被去除。 漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

公开(公告)号：US08927869B2

公开(公告)日：2015-01-06

申请号：US13444343

申请日：2012-04-11

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H05K1/00

CPC classification number: H01L24/05 ,  H01B3/306 ,  H01B3/307 ,  H01L21/02118 ,  H01L21/76877 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/48

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Abstract translation: 公开了使用有机绝缘材料的引线键合半导体结构和制造方法。 该方法包括在有机绝缘体层中形成金属布线层。 该方法还包括在有机绝缘体层上形成保护层。 该方法还包括在金属布线层上的有机绝缘体层中形成通孔。 该方法还包括在通孔中和保护层上沉积金属层。 该方法还包括用对有机绝缘体层有害的蚀刻化学物图案化金属层。

公开(公告)号：US08766439B2

公开(公告)日：2014-07-01

申请号：US12634741

申请日：2009-12-10

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/12

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract translation: 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US08765595B2

公开(公告)日：2014-07-01

申请号：US13345120

申请日：2012-01-06

Applicant: Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee ,  Xiao H. Liu

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee ,  Xiao H. Liu

IPC: H01L21/4763

CPC classification number: H01L23/5227 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

Abstract translation: BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。 在第一线退火之后，形成与第一线垂直对准的第二线。 形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。

公开(公告)号：US08679863B2

公开(公告)日：2014-03-25

申请号：US13420637

申请日：2012-03-15

Applicant: Jeffrey P. Gambino ,  Derrick Liu ,  Dale W. Martin ,  Gerd Pfeiffer

Inventor： Jeffrey P. Gambino ,  Derrick Liu ,  Dale W. Martin ,  Gerd Pfeiffer

IPC: H01L21/00

CPC classification number: H01L22/14 ,  H01L21/324 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.

Abstract translation: 提供了微调衬底电阻率的方法。 该方法包括测量退火处理之后的衬底的电阻率，并且微调随后的退火工艺以实现衬底的目标电阻率。 微调基于测量的电阻率。

公开(公告)号：US08618588B2

公开(公告)日：2013-12-31

申请号：US12915888

申请日：2010-10-29

Applicant: Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

Inventor： Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H04N5/238 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14685 ,  H04N5/3591

Abstract: A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

Abstract translation: 防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

公开(公告)号：US08592244B2

公开(公告)日：2013-11-26

申请号：US13189961

申请日：2011-07-25

Applicant: Jeffrey P. Gambino ,  Robert K. Leidy ,  Mark D. Levy

Inventor： Jeffrey P. Gambino ,  Robert K. Leidy ,  Mark D. Levy

IPC: H01L21/00

CPC classification number: H01L27/14623 ,  H01L27/14636 ,  H01L27/14687

Abstract: Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel.

Abstract translation: 提供了具有不透明掩模层的像素传感器单元和制造方法。 该方法包括在像素传感器单元的至少一个有源像素和至少一个暗像素的上方形成透明层。 该方法还包括在至少一个暗像素上的透明层中形成不透明区域。

公开(公告)号：US08569888B2

公开(公告)日：2013-10-29

申请号：US13114079

申请日：2011-05-24

Applicant: Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

Abstract translation: 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

公开(公告)号：US20130269974A1

公开(公告)日：2013-10-17

申请号：US13444343

申请日：2012-04-11

Applicant: Timothy H. DAUBENSPECK ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Christopher D. MUZZY ,  Wolfgang SAUTER ,  Timothy D. SULLIVAN

Inventor： Timothy H. DAUBENSPECK ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Christopher D. MUZZY ,  Wolfgang SAUTER ,  Timothy D. SULLIVAN

IPC: H01B3/30 ,  H01B13/00 ,  H01B13/06 ,  H01B7/00

CPC classification number: H01L24/05 ,  H01B3/306 ,  H01B3/307 ,  H01L21/02118 ,  H01L21/76877 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/48

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.