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    SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF 有权
    半导体器件及其测试方法

    公开(公告)号：US20130107646A1

    公开(公告)日：2013-05-02

    申请号：US13333715

    申请日：2011-12-21

    申请人： Bo-Yeun KIM ,  Ji-Eun JANG

    发明人： Bo-Yeun KIM ,  Ji-Eun JANG

    IPC分类号： G11C7/00

    CPC分类号： G11C29/785 ,  G11C29/802 ,  G11C2029/4402

    摘要： A semiconductor device comprises a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.

    摘要翻译： 半导体器件分别包括响应于多个选择信号被激活的多个单元块，预选择信号发生器被配置为分别产生与单元块相对应的多个预选信号，并激活至少两个 通过在多测试模式中解码地址来选择预选信号，选择信号控制器被配置为响应于多个预选信号选择性地激活多个选择信号，并且控制所激活的选择信号的有效期，以便不 以及判定电路，其被配置为响应于所存储的修复信息和所述多个选择信号来确定响应于所激活的选择信号而被激活的单元块是否被修复。

    Semiconductor memory device and method for testing the same
    3.
    发明授权
    Semiconductor memory device and method for testing the same 有权
    半导体存储器件及其测试方法

    公开(公告)号：US08296610B2

    公开(公告)日：2012-10-23

    申请号：US12181700

    申请日：2008-07-29

    申请人： Ji-Eun Jang ,  Seok-Cheol Yoon

    发明人： Ji-Eun Jang ,  Seok-Cheol Yoon

    IPC分类号： G06F11/00

    CPC分类号： G11C29/48 ,  G11C7/1006 ,  G11C7/1078 ,  G11C29/1201 ,  G11C29/14

    摘要： A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.

    摘要翻译： 一种半导体存储器件，包括对准单元，被配置为对准从外部接收的数据，分别对应于对准的数据的多个数据输入/输出线以及重新对准单元，其被配置为改变数据和数据输入/输出线之间的对应关系 响应于测试模式中的一个或多个改变信号。 用于测试半导体存储器件的方法包括使用测试装置串联输入数据，并行地对齐串行数据，以及响应于一个或多个改变信号重新对准并行数据。

    Simplified power-down mode control circuit utilizing active mode operation control signals
    5.
    发明授权
    Simplified power-down mode control circuit utilizing active mode operation control signals 有权
    利用有源模式操作控制信号的简化掉电模式控制电路

    公开(公告)号：US07826304B2

    公开(公告)日：2010-11-02

    申请号：US12181426

    申请日：2008-07-29

    申请人： Ji Eun Jang

    发明人： Ji Eun Jang

    IPC分类号： G11C8/00

    CPC分类号： G11C5/14 ,  G11C5/144 ,  G11C7/22 ,  G11C2207/2227

    摘要： A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level.

    摘要翻译： 当在活动模式操作期间接收到掉电模式进入命令时，断电控制电路利用在主动模式操作中采用的控制信号来操作。 电路简化，在降低功耗的同时，需要较少的面积来设计控制电路。 半导体存储装置中的掉电控制电路至少包括时钟使能缓冲器单元，外部时钟缓冲器单元，锁存单元，控制电路，用于通过使用控制信号控制在主动模式操作中使用的内部工作时钟 在活动模式操作期间接收掉电模式输入命令时的主动模式操作;以及时钟使能发生电路，用于通过使用时钟控制信号输出用于使得能够进入掉电模式的时钟使能信号，当外部 时钟脉冲信号为低电平。

    On die termination device and semiconductor memory device including the same
    6.
    发明授权
    On die termination device and semiconductor memory device including the same 有权
    在晶片终端器件和包括其的半导体存储器件中

    公开(公告)号：US07825683B2

    公开(公告)日：2010-11-02

    申请号：US12181628

    申请日：2008-07-29

    申请人： Ki-Ho Kim ,  Ji-Eun Jang

    发明人： Ki-Ho Kim ,  Ji-Eun Jang

    IPC分类号： H03K17/16

    CPC分类号： G11C5/063 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

    摘要： On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes.

    摘要翻译： 在终端（ODT）设备上，可以减少用于传送校准码的行数，以减少包括ODT设备在内的芯片的尺寸。 ODT装置包括：校准电路，被配置为产生用于确定终止电阻的校准码;计数电路，被配置为产生随时间增加的计数码。 依次配置设备的传送电路以响应于计数代码传送校准代码。 接收电路被顺序配置以响应于计数代码从传送电路接收校准码。 该器件的终端电阻电路被配置为使用根据校准码确定的电阻来执行阻抗匹配。

    Semiconductor memory device and method for driving the same
    7.
    发明授权
    Semiconductor memory device and method for driving the same 有权
    半导体存储器件及其驱动方法

    公开(公告)号：US07660171B2

    公开(公告)日：2010-02-09

    申请号：US11823878

    申请日：2007-06-29

    申请人： Ji-Eun Jang

    发明人： Ji-Eun Jang

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4093

    摘要： A semiconductor memory device includes: a first count unit for counting a delayed locked loop (DLL) clock in response to a clock enable signal; a first delay unit for delaying the clock enable signal for a delay time which corresponds to a delay amount of a delay model included in a DLL circuit; a second count unit for counting an external clock in response to the delayed clock enable signal; a comparison unit for comparing an output of the first count unit with an output of the second count unit in order to generate a latency signal; and an output enable signal generation unit for generating an output enable signal by using the latency signal.

    摘要翻译： 半导体存储器件包括：第一计数单元，用于响应于时钟使能信号对延迟锁定环（DLL）时钟进行计数; 第一延迟单元，用于将对应于包括在DLL电路中的延迟模型的延迟量的延迟时间延迟所述时钟使能信号; 第二计数单元，用于响应延迟的时钟使能信号对外部时钟进行计数; 比较单元，用于将第一计数单元的输出与第二计数单元的输出进行比较，以产生等待时间信号; 以及输出使能信号生成单元，用于通过使用等待时间信号来产生输出使能信号。

    DATA OUTPUT CONTROL CIRCUIT
    8.
    发明申请
    DATA OUTPUT CONTROL CIRCUIT 失效
    数据输出控制电路

    公开(公告)号：US20090116313A1

    公开(公告)日：2009-05-07

    申请号：US11967595

    申请日：2007-12-31

    申请人： Ji-Eun JANG

    发明人： Ji-Eun JANG

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1066

    摘要： A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to an active signal, and to determine an output timing of data corresponding to a read command by counting the system clock and a DLL clock outputted from the DLL circuit 0 when the DLL circuit 0 is disabled, without compensating the delay amount.

    摘要翻译： 数据输出控制电路包括：数据输出控制电路，被配置为当在半导体存储器件退出复位状态的状态下使能延迟锁定环（DLL）电路时，补偿时钟路径上的系统时钟的延迟量 响应于活动信号，并且在DLL电路0被禁用时，通过对系统时钟和从DLL电路0输出的DLL时钟进行计数来确定与读命令相对应的数据的输出定时，而不补偿延迟量。

    Semiconductor memory device
    9.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20090003096A1

    公开(公告)日：2009-01-01

    申请号：US12003680

    申请日：2007-12-31

    申请人： Kyung-Whan Kim ,  Ji-Eun Jang

    发明人： Kyung-Whan Kim ,  Ji-Eun Jang

    IPC分类号： G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/1045 ,  G11C11/4076 ,  G11C11/408 ,  G11C2207/2254

    摘要： A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.

    摘要翻译： 提供半导体存储器件以改善tAA特性。 半导体存储器件包括：识别信号产生单元，用于产生表示半导体存储器件的写入操作的第一鉴别信号; 选择延迟单元，用于响应于第二鉴别信号延迟命令组信号; 以及熔丝单元，用于基于所述第一判别信号产生所述第二判别信号，所述第二判别信号确定所述选择延迟单元是否响应于所述第一判别信号有选择地延迟所述命令组信号。

    Simplified power-down mode control circuit utilizing active mode operation control signals
    10.
    发明授权
    Simplified power-down mode control circuit utilizing active mode operation control signals 有权
    利用有源模式操作控制信号的简化掉电模式控制电路

    公开(公告)号：US07420873B2

    公开(公告)日：2008-09-02

    申请号：US11652786

    申请日：2007-01-12

    申请人： Ji Eun Jang

    发明人： Ji Eun Jang

    IPC分类号： G11C7/22 ,  G11C8/18

    CPC分类号： G11C5/14 ,  G11C5/144 ,  G11C7/22 ,  G11C2207/2227

    摘要： A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level.

    摘要翻译： 当在活动模式操作期间接收到掉电模式进入命令时，断电控制电路利用在主动模式操作中采用的控制信号来操作。 电路简化，在降低功耗的同时，需要较少的面积来设计控制电路。 半导体存储装置中的掉电控制电路至少包括时钟使能缓冲器单元，外部时钟缓冲器单元，锁存单元，控制电路，用于通过使用控制信号控制在主动模式操作中使用的内部工作时钟 在活动模式操作期间接收掉电模式输入命令时的主动模式操作;以及时钟使能发生电路，用于通过使用时钟控制信号输出用于使得能够进入掉电模式的时钟使能信号，当外部 时钟脉冲信号为低电平。