公开(公告)号：US20060095878A1

公开(公告)日：2006-05-04

申请号：US11005647

申请日：2004-12-06

申请人： Jiann-Tsuen Chen ,  Jean-Huang Chen

发明人： Jiann-Tsuen Chen ,  Jean-Huang Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to generate test and expected data for a controller and/or a data processor in a multi-field video processor hardware model. The design verification architecture may provide test data via stimulus feeders and may compare simulated and expected data in result checkers. When the controller is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor control data flow implementation. When the data processor is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor video data flow implementation.

公开(公告)号：US5914725A

公开(公告)日：1999-06-22

申请号：US612105

申请日：1996-03-07

申请人： Alexander G. MacInnis ,  Jiann-Tsuen Chen

发明人： Alexander G. MacInnis ,  Jiann-Tsuen Chen

IPC分类号： G06T3/40 ,  G06T11/00

CPC分类号： G06T3/4007

摘要： Interpolating a low or medium resolution image to a higher resolution image using a pixel replication and averaging technique. An overlay image having pixels of a first display resolution and a plurality of alpha blending values each indicating the degree of blending with a background image is interpolated to the resolution of the background image. In addition to interpolating pixel values, alpha blending values are themselves interpolated and multiplied by corresponding overlay pixel values prior to being blended with the background image.

摘要翻译： 使用像素复制和平均技术将低或中分辨率图像插值到较高分辨率的图像。 具有第一显示分辨率的像素和每个表示与背景图像的混合程度的多个α混合值的重叠图像被内插到背景图像的分辨率。 除了内插像素值之外，在混合背景图像之前，alpha混合值本身被内插并乘以相应的重叠像素值。

公开(公告)号：US07418625B2

公开(公告)日：2008-08-26

申请号：US10953463

申请日：2004-09-29

申请人： Jiann-Tsuen Chen ,  Guang-Ting Shih

发明人： Jiann-Tsuen Chen ,  Guang-Ting Shih

IPC分类号： G06F11/00

CPC分类号： G06F9/524 ,  H04N9/44 ,  H04N9/78

摘要： Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential deadlock state in a distribute and merge data processing system. An actual deadlock state may be detected once the potential deadlock state is identified. The detected actual deadlock state may be indicated by generating a signal. The method may comprise initiating recovery from deadlock conditions by generating at least one signal that indicates when data is accepted in response to the indication of the actual deadlock state.

摘要翻译： 可以在用于处理数据处理系统中的死锁状态的方法和系统中找到本发明的某些实施例。 方法的方面可以包括识别分布和合并数据处理系统中的潜在的死锁状态。 一旦识别到潜在的死锁状态，就可以检测出实际的死锁状态。 可以通过生成信号来指示检测到的实际死锁状态。 该方法可以包括通过产生响应于实际死锁状态的指示来指示何时接收数据的至少一个信号来从死锁状态启动恢复。

公开(公告)号：US20060069542A1

公开(公告)日：2006-03-30

申请号：US11005092

申请日：2004-12-06

申请人： Jiann-Tsuen Chen ,  Jean-Huang Chen

发明人： Jiann-Tsuen Chen ,  Jean-Huang Chen

IPC分类号： G06F9/45

CPC分类号： H04N7/012 ,  G09G2310/0229 ,  G09G2320/0261 ,  H04N7/0112

摘要： In a video system, a method and system for efficient design verification of a motion adaptive deinterlacer (MAD) are provided. A MAD reference model may be configured via a configuration file to generate test parameters for the verification of a MAD hardware model. Test-bench interface drivers and a verification monitor may be utilized to transfer test parameters to the MAD hardware model and to verify simulated results. Modes of verification may comprise a normal mode, a pixel processing mode, and a field controller mode. During the normal mode, simulated pixel information and register settings generated by the pixel processor and field controller in the MAD hardware model may be compared to expected pixel information and register settings generated by the MAD reference model. During the pixel processing mode, expected and simulated pixel information may be compared. During the field controller mode, expected and simulated register settings may be compared.

公开(公告)号：US20060061689A1

公开(公告)日：2006-03-23

申请号：US10953463

申请日：2004-09-29

申请人： Jiann-Tsuen Chen ,  Guang-Ting Shih

发明人： Jiann-Tsuen Chen ,  Guang-Ting Shih

IPC分类号： H04N5/21 ,  H04N9/77

CPC分类号： G06F9/524 ,  H04N9/44 ,  H04N9/78

摘要： Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential deadlock state in a distribute and merge data processing system. An actual deadlock state may be detected once the potential deadlock state is identified. The detected actual deadlock state may be indicated by generating a signal. The method may comprise initiating recovery from deadlock conditions by generating at least one signal that indicates when data is accepted in response to the indication of the actual deadlock state.

摘要翻译： 可以在用于处理数据处理系统中的死锁状态的方法和系统中找到本发明的某些实施例。 方法的方面可以包括识别分布和合并数据处理系统中的潜在的死锁状态。 一旦识别到潜在的死锁状态，就可以检测出实际的死锁状态。 可以通过生成信号来指示检测到的实际死锁状态。 该方法可以包括通过产生响应于实际死锁状态的指示来指示何时接收数据的至少一个信号来从死锁状态启动恢复。

公开(公告)号：US6023302A

公开(公告)日：2000-02-08

申请号：US612162

申请日：1996-03-07

申请人： Alexander G. MacInnis ,  Jiann-Tsuen Chen

发明人： Alexander G. MacInnis ,  Jiann-Tsuen Chen

IPC分类号： H04N9/75 ,  H04N9/74

CPC分类号： H04N9/75

摘要： A graphics blending feature for a terminal such as a home communication terminal (HCT) allows an overlay image to be selectively blended with a background image through the use of a chroma key function and one or more alpha control bits. The chroma key function is used to determine whether the overlay will be completely transparent or not, and the one or more alpha control bits are used to look up a larger alpha value used to blend the overlay and background images. By using a small number of alpha control bits to retrieve a larger alpha value for blending, memory requirements per pixel are reduced. The chroma key function may be implemented by comparing each overlay pixel value to a chroma value and, responsive to a match, making the overlay pixel transparent (i.e., no blending occurs). A dithering function is included in various embodiments to smooth out the resulting image.

摘要翻译： 用于诸如家庭通信终端（HCT）的终端的图形混合特征允许通过使用色度键功能和一个或多个阿尔法控制位来将叠加图像与背景图像选择性地混合。 色度键功能用于确定叠加层是否完全透明，并且一个或多个Alpha控制位用于查找用于混合叠加和背景图像的较大α值。 通过使用少量的Alpha控制位来获取较大的Alpha值进行混合，每像素的内存要求降低。 可以通过将每个覆盖像素值与色度值进行比较并且响应于匹配使得覆盖像素透明（即，不发生混合）来实现色度键功能。 在各种实施例中包括抖动功能以平滑所得到的图像。

公开(公告)号：US07636834B2

公开(公告)日：2009-12-22

申请号：US10302489

申请日：2002-11-21

申请人： Chengfuh Jeffrey Tang ,  Jiann-Tsuen Chen

发明人： Chengfuh Jeffrey Tang ,  Jiann-Tsuen Chen

IPC分类号： G06F13/00 ,  G11C7/10 ,  G06F5/00

CPC分类号： G06F5/10 ,  G06F5/12 ,  G06F5/14 ,  G06F13/1673 ,  G06F2205/102

摘要： Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

摘要翻译： 本发明的各方面可以包括逐渐递减或增加与诸如FIFO缓冲器（310）的数据缓冲器相关联的写指针（370），直到达到写指针（370）的复位值，以响应于指示数据 由灰色代码计数器控制的缓冲区为空。 此外，与数据缓冲器（310）相关联的读指针（380）可以逐渐递增或递减，直到响应于由灰码计数器控制的数据缓冲器的指示达到读指针（380）的复位值 已满。 数据缓冲器可以是先入先出（FIFO）缓冲器，例如可以异步计时的FIFO缓冲器310。 数据缓冲器可以适于缓冲视频，语音和数据的任何一种或组合。

公开(公告)号：US07584380B2

公开(公告)日：2009-09-01

申请号：US10981178

申请日：2004-11-04

申请人： Jiann-Tsuen Chen ,  Guang-Ting Shih

发明人： Jiann-Tsuen Chen ,  Guang-Ting Shih

IPC分类号： G06F11/00

CPC分类号： H04L47/10 ,  H04L43/18 ,  H04L69/12

摘要： Certain embodiments for debugging mechanism for flow control based designs may comprise a debugging interface module between a transmitter and a receiver, all integrated on a chip. At least one debugging entity, which may be on the chip or off the chip, may indicate to the debugging interface module to initiate debug mode via command signals. In debug mode, the control signals between the transmitter and the receiver may be intercepted by the debugging interface module to halt normal data flow from the transmitter to the receiver. The debugging entity may then transmit data to the receiver, while the transmitter is disabled, or receive data transmitted by the transmitter, while the receiver is disabled. When the debugging entity indicates to the debugging interface module to end debug mode, normal data flow may continue, and the debugging interface module may appear transparent to the data flow.

摘要翻译： 用于基于流控制的设计的调试机制的某些实施例可以包括全部集成在芯片上的发射机和接收机之间的调试接口模块。 至少一个可能在芯片上或芯片上的调试实体可以向调试接口模块指示通过命令信号启动调试模式。 在调试模式下，发射机和接收机之间的控制信号可能被调试接口模块拦截，以阻止从发射机到接收机的正常数据流。 然后，当接收机被禁用时，调试实体可以在发射机被禁用的同时或者接收由发射机发射的数据的同时向接收机发送数据。 当调试实体向调试接口模块指示结束调试模式时，正常的数据流可能会继续，调试接口模块可能对数据流显示为透明。

公开(公告)号：US20060069954A1

公开(公告)日：2006-03-30

申请号：US10981178

申请日：2004-11-04

申请人： Jiann-Tsuen Chen ,  Guang-Ting Shih

发明人： Jiann-Tsuen Chen ,  Guang-Ting Shih

IPC分类号： G06F11/00

CPC分类号： H04L47/10 ,  H04L43/18 ,  H04L69/12

摘要： Certain embodiments for debugging mechanism for flow control based designs may comprise a debugging interface module between a transmitter and a receiver, all integrated on a chip. At least one debugging entity, which may be on the chip or off the chip, may indicate to the debugging interface module to initiate debug mode via command signals. In debug mode, the control signals between the transmitter and the receiver may be intercepted by the debugging interface module to halt normal data flow from the transmitter to the receiver. The debugging entity may then transmit data to the receiver, while the transmitter is disabled, or receive data transmitted by the transmitter, while the receiver is disabled. When the debugging entity indicates to the debugging interface module to end debug mode, normal data flow may continue, and the debugging interface module may appear transparent to the data flow.

公开(公告)号：US5903281A

公开(公告)日：1999-05-11

申请号：US612104

申请日：1996-03-07

申请人： Jiann-tsuen Chen ,  Alexandar G. MacInnis ,  Ken Morse

发明人： Jiann-tsuen Chen ,  Alexandar G. MacInnis ,  Ken Morse

IPC分类号： G06F9/38 ,  G09G5/393

CPC分类号： G09G5/393 ,  G06F9/3879 ,  G09G2340/125

摘要： An improved graphical manipulation technique for a home communication terminal (HCT) includes a linked-list of commands controlling various video operations in an application specific integrated circuit (ASIC). After each command has been implemented by the ASIC, the ASIC proceeds to the next command without interrupting a host processor. Accordingly, the linked-list eliminates the need of the host processor to continually process interrupts at the completion of each instruction. The linked-list command structure aids in intensive video operations including bit block transfers, video capture, and video display.

摘要翻译： 用于家庭通信终端（HCT）的改进的图形操作技术包括控制专用集成电路（ASIC）中的各种视频操作的命令的链表。 在每个命令已由ASIC实现之后，ASIC进行到下一个命令而不中断主机处理器。 因此，链表不需要主机处理器在每个指令完成时连续处理中断。 链表指令结构有助于密集的视频操作，包括位块传输，视频采集和视频显示。