公开(公告)号：US5565700A

公开(公告)日：1996-10-15

申请号：US426491

申请日：1995-04-20

申请人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

发明人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

摘要翻译： 描述了新的表面反掺杂轻掺杂源极和漏极集成电路场效应晶体管器件。 在硅衬底上形成栅氧化硅层。 一层多晶硅沉积在栅极氧化硅层上并被蚀刻以形成栅电极结构。 以倾斜角度执行第一离子注入，以在半导体衬底中形成轻掺杂漏极区域，其中轻掺杂漏极区域被栅电极结构部分地重叠。 以比第一离子注入更大的倾斜角度和更低的能量执行第二离子注入，其中第二离子注入反掺杂轻掺杂的漏极区的表面以形成非常轻掺杂的漏极层，从而使轻掺杂漏极区 埋葬地区。 氧化硅薄层沉积在多晶硅栅电极结构的表面上，并被各向异性蚀刻以在多晶硅栅电极结构的侧壁上形成超薄间隔物。 执行没有倾斜角的第三离子注入以完成轻掺杂漏极区的形成。 在基板的所有表面上沉积一层胶层，然后流动，随后进行金属化和钝化以完成集成电路的制造。

公开(公告)号：US5308780A

公开(公告)日：1994-05-03

申请号：US94990

申请日：1993-07-22

申请人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

发明人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method of forming an integrated circuit field effect transistor with surface counter-doped lightly doped drain regions is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

摘要翻译： 描述了一种形成具有表面反掺杂轻掺杂漏极区域的集成电路场效应晶体管的方法。 在硅衬底上形成栅氧化硅层。 一层多晶硅沉积在栅极氧化硅层上并被蚀刻以形成栅电极结构。 以倾斜角度执行第一离子注入，以在半导体衬底中形成轻掺杂漏极区域，其中轻掺杂漏极区域被栅电极结构部分地重叠。 以比第一离子注入更大的倾斜角度和更低的能量执行第二离子注入，其中第二离子注入反掺杂轻掺杂的漏极区的表面以形成非常轻掺杂的漏极层，从而使轻掺杂漏极区 埋葬地区。 氧化硅薄层沉积在多晶硅栅电极结构的表面上，并被各向异性蚀刻以在多晶硅栅电极结构的侧壁上形成超薄间隔物。 执行没有倾斜角的第三离子注入以完成轻掺杂漏极区的形成。 在基板的所有表面上沉积一层胶层，然后流动，随后进行金属化和钝化以完成集成电路的制造。