Input device for an electronic device and electronic device having the same
    1.
    发明授权
    Input device for an electronic device and electronic device having the same 有权
    用于电子设备的输入设备和具有该电子设备的电子设备

    公开(公告)号:US07996050B2

    公开(公告)日:2011-08-09

    申请号:US11711662

    申请日:2007-02-28

    IPC分类号: H04M1/00

    CPC分类号: H01H19/003

    摘要: An input device for an electronic device is provided that includes a base, a frame pivotally connected to the base, a roller member rotatably supported by the frame, and at least one button pivotally connected at a side of the base. An electronic device is also provided that includes a first body, a second body pivotally attached to the first body, and an input device located in the first body.

    摘要翻译: 提供一种电子设备的输入装置,其包括基座,可枢转地连接到基座的框架,由框架可旋转地支撑的滚子构件以及在基座侧面枢转地连接的至少一个按钮。 还提供一种电子设备,其包括第一主体,可枢转地附接到第一主体的第二主体和位于第一主体中的输入装置。

    METHOD OF MANUFACTURING AN INSTANT PULSE FILTER USING ANODIC OXIDATION AND INSTANT PULSE FILTER MANUFACTURED BY SAID METHOD
    2.
    发明申请
    METHOD OF MANUFACTURING AN INSTANT PULSE FILTER USING ANODIC OXIDATION AND INSTANT PULSE FILTER MANUFACTURED BY SAID METHOD 失效
    使用阳极氧化制造瞬时脉冲滤波器的方法和由方法制造的瞬时脉冲滤波器

    公开(公告)号:US20110133854A1

    公开(公告)日:2011-06-09

    申请号:US13057493

    申请日:2009-04-03

    IPC分类号: H03H7/00 C23C28/00

    摘要: The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external environment; and a seventh step for forming an external electrode on both sides of the substrate in which the protective film layer is formed.

    摘要翻译: 根据本发明的瞬时脉冲滤波器,其可能导致半导体器件的故障或短寿命,使用铝阳极氧化制成,包括:第一步骤,用于在上部形成铝薄膜层 绝缘体基板; 通过阳极氧化氧化铝薄膜层来形成具有孔的氧化铝薄膜层的第二步骤; 第三步骤,用于在用于填充孔的铝薄膜层的上侧上沉积金属材料; 第四步,通过除去除了孔之外沉积的金属材料,在氧化铝薄膜层的内部形成纳米棒; 在具有纳米棒的氧化铝薄膜层的上侧形成内部电极的第五步骤; 为了保护氧化铝薄膜层和内部电极免受外部环境的影响,在其上侧形成保护膜层的第六步骤; 以及在其上形成有保护膜层的基板的两侧上形成外部电极的第七步骤。

    Input device for an electronic device and electronic device having the same
    3.
    发明申请
    Input device for an electronic device and electronic device having the same 有权
    用于电子设备的输入设备和具有该电子设备的电子设备

    公开(公告)号:US20070210828A1

    公开(公告)日:2007-09-13

    申请号:US11711662

    申请日:2007-02-28

    IPC分类号: H03K19/177

    CPC分类号: H01H19/003

    摘要: An input device for an electronic device is provided that includes a base, a frame pivotally connected to the base, a roller member rotatably supported by the frame, and at least one button pivotally connected at a side of the base. An electronic device is also provided that includes a first body, a second body pivotally attached to the first body, and an input device located in the first body.

    摘要翻译: 提供一种电子设备的输入装置,其包括基座,可枢转地连接到基座的框架,由框架可旋转地支撑的滚子构件以及在基座侧面枢转地连接的至少一个按钮。 还提供一种电子设备,其包括第一主体,可枢转地附接到第一主体的第二主体和位于第一主体中的输入装置。

    Semiconductor memory device having local data line pair with delayed precharge voltage application point
    4.
    发明授权
    Semiconductor memory device having local data line pair with delayed precharge voltage application point 失效
    半导体存储器件具有延迟的预充电电压施加点的本地数据线对

    公开(公告)号:US07248517B2

    公开(公告)日:2007-07-24

    申请号:US11128878

    申请日:2005-05-14

    IPC分类号: G11C7/00

    CPC分类号: G11C11/4094 G11C11/4097

    摘要: Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write control signal, thus lengthening the interval starting from the time when data on a pair of bit lines are amplified to the time when a supply voltage is applied to a pair of local data lines. Therefore, according to the semiconductor memory device of the present invention, the time when the supply voltage is applied to the pair of local data lines is the time after data have sufficiently stabilized on the pair of bit lines. Therefore, the semiconductor memory device of the present invention prevents the stabilization speed of the pair of bit lines and the pair of local data lines from decreasing, thus consequently improving the operating speed of the semiconductor memory device.

    摘要翻译: 这里公开了具有延迟的预充电电压施加点的一对本地数据线的半导体存储器件。 本发明的半导体存储器件包括用于延迟块写入控制信号的激活时间的延迟块,从而延长从一对位线上的数据被放大到电源电压为时间的时间开始的间隔 应用于一对本地数据线。 因此,根据本发明的半导体存储器件,向一对本地数据线施加电源电压的时间是数据在一对位线上已经足够稳定的时间。 因此,本发明的半导体存储器件防止一对位线和一对本地数据线的稳定化速度降低,从而提高半导体存储器件的工作速度。

    On-die termination circuit, method of controlling the same, and ODT synchronous buffer
    5.
    发明申请
    On-die termination circuit, method of controlling the same, and ODT synchronous buffer 失效
    片上终端电路,控制方法和ODT同步缓冲器

    公开(公告)号:US20080204071A1

    公开(公告)日:2008-08-28

    申请号:US12071848

    申请日:2008-02-27

    IPC分类号: H03K19/003 G11C7/00 G11C8/00

    摘要: An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.

    摘要翻译: 片上终端(ODT)电路可以包括ODT同步缓冲器和/或ODT门。 ODT同步缓冲器可以被配置为与延迟锁定到外部时钟信号的第一时钟信号同步地从外部ODT命令生成同步ODT命令。 ODT门可以被配置为基于延迟锁定到外部时钟信号和同步ODT命令的第二时钟信号来产生用于控制ODT的信号。 可以在第二时钟信号的禁用时段中生成同步ODT命令。

    Method and device for controlling internal power voltage, and semiconductor memory device having the same
    6.
    发明申请
    Method and device for controlling internal power voltage, and semiconductor memory device having the same 有权
    用于控制内部电源电压的方法和装置,以及具有该功率电压的半导体存储器件

    公开(公告)号:US20050275986A1

    公开(公告)日:2005-12-15

    申请号:US11154076

    申请日:2005-06-15

    申请人: Jin-Hyung Cho

    发明人: Jin-Hyung Cho

    IPC分类号: G11C5/14 G11C11/4074 H02H3/24

    摘要: In an embodiment, a device controls an internal power voltage in a semiconductor device. The device uses internal and external power voltages during a power-up period, and includes a power-up flag signal generator and a control circuit. The power-up flag signal generator generates a power-up flag signal based on the external power voltage. The control circuit provides a first internal power voltage to a peripheral circuit of the semiconductor device. During power-up the first internal power voltage varies according to a level of the external power voltage in response to the power-up flag signal having a first logic level. Accordingly, an internal power voltage may have a linear power-up slope during the power-up period and an initialization failure of any latch circuits in the peripheral circuit may be avoided. Also, power consumption of the latch circuits is reduced.

    摘要翻译: 在一个实施例中,设备控制半导体器件中的内部电源电压。 该装置在上电期间使用内部和外部电源电压,并且包括上电标志信号发生器和控制电路。 上电标志信号发生器基于外部电源电压产生上电标志信号。 控制电路向半导体器件的外围电路提供第一内部电源电压。 在上电期间,响应于具有第一逻辑电平的上电标志信号,第一内部电源电压根据外部电源电压的电平而变化。 因此,内部电源电压在加电期间可能具有线性上电斜率,并且可以避免外围电路中的任何锁存电路的初始化故障。 此外,锁存电路的功耗降低。

    Method of manufacturing an instant pulse filter using anodic oxidation and instant pulse filter manufactured by said method
    7.
    发明授权
    Method of manufacturing an instant pulse filter using anodic oxidation and instant pulse filter manufactured by said method 失效
    使用所述方法制造的使用阳极氧化的瞬时脉冲滤波器和即时脉冲滤波器的方法

    公开(公告)号:US08129745B2

    公开(公告)日:2012-03-06

    申请号:US13057493

    申请日:2009-04-03

    IPC分类号: H01L21/00

    摘要: The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external environment; and a seventh step for forming an external electrode on both sides of the substrate in which the protective film layer is formed.

    摘要翻译: 根据本发明的瞬时脉冲滤波器,其可能导致半导体器件的故障或短寿命,使用铝阳极氧化制成,包括:第一步骤,用于在上部形成铝薄膜层 绝缘体基板; 通过阳极氧化氧化铝薄膜层来形成具有孔的氧化铝薄膜层的第二步骤; 第三步骤,用于在用于填充孔的铝薄膜层的上侧上沉积金属材料; 第四步,通过除去除了孔之外沉积的金属材料,在氧化铝薄膜层的内部形成纳米棒; 在具有纳米棒的氧化铝薄膜层的上侧形成内部电极的第五步骤; 为了保护氧化铝薄膜层和内部电极免受外部环境的影响,在其上侧形成保护膜层的第六步骤; 以及在其上形成有保护膜层的基板的两侧上形成外部电极的第七步骤。

    Input/output buffer having reduced skew and methods of operation
    8.
    发明授权
    Input/output buffer having reduced skew and methods of operation 失效
    具有减少的偏斜和操作方法的输入/输出缓冲器

    公开(公告)号:US06777985B2

    公开(公告)日:2004-08-17

    申请号:US10431980

    申请日:2003-05-08

    IPC分类号: H03K5153

    CPC分类号: H03K19/00323 H03K19/00384

    摘要: A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.

    摘要翻译: 缓冲器具有接收外部信号,参考电压并输出放大信号的放大器。 放大的信号响应于外部信号和参考电压之间的差异。 反相器接收放大的信号并产生反相信号。 电压供给电路被配置为响应于参考电压向调节器提供调整的电源电压。 接地电压供应电路被配置为响应于参考电压向调节器提供调整的接地电压。

    Semiconductor device generating a test voltage for a wafer burn-in test and method thereof
    9.
    发明授权
    Semiconductor device generating a test voltage for a wafer burn-in test and method thereof 有权
    产生晶片老化测试的测试电压的半导体器件及其方法

    公开(公告)号:US07480196B2

    公开(公告)日:2009-01-20

    申请号:US11651973

    申请日:2007-01-11

    IPC分类号: G11C7/00

    摘要: A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.

    摘要翻译: 公开了一种用于生成晶片老化测试的测试电压的半导体器件及其方法。 为了产生用于晶片老化测试的测试电压,可以响应于来自外部晶片老化测试装置的电源电压而产生控制信号。 可以通过使用内部电压驱动电路来响应于控制信号产生辅助电压。 可以通过组合电源电压和辅助电压来产生测试电压。

    Semiconductor memory device having local data line pair with delayed precharge voltage application point
    10.
    发明申请
    Semiconductor memory device having local data line pair with delayed precharge voltage application point 失效
    半导体存储器件具有延迟的预充电电压施加点的本地数据线对

    公开(公告)号:US20060120182A1

    公开(公告)日:2006-06-08

    申请号:US11128878

    申请日:2005-05-14

    IPC分类号: G11C7/00

    CPC分类号: G11C11/4094 G11C11/4097

    摘要: Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write control signal, thus lengthening the interval starting from the time when data on a pair of bit lines are amplified to the time when a supply voltage is applied to a pair of local data lines. Therefore, according to the semiconductor memory device of the present invention, the time when the supply voltage is applied to the pair of local data lines is the time after data have sufficiently stabilized on the pair of bit lines. Therefore, the semiconductor memory device of the present invention prevents the stabilization speed of the pair of bit lines and the pair of local data lines from decreasing, thus consequently improving the operating speed of the semiconductor memory device.

    摘要翻译: 这里公开了具有延迟的预充电电压施加点的一对本地数据线的半导体存储器件。 本发明的半导体存储器件包括用于延迟块写入控制信号的激活时间的延迟块,从而延长从一对位线上的数据被放大到电源电压为时间的时间开始的间隔 应用于一对本地数据线。 因此,根据本发明的半导体存储器件,向一对本地数据线施加电源电压的时间是数据在一对位线上已经足够稳定的时间。 因此,本发明的半导体存储器件防止一对位线和一对本地数据线的稳定化速度降低,从而提高半导体存储器件的工作速度。