公开(公告)号：US20160293627A1

公开(公告)日：2016-10-06

申请号：US15087127

申请日：2016-03-31

申请人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

发明人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC分类号： H01L27/115 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L27/11565

摘要： Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

摘要翻译： 提供半导体存储器件及其制造方法。 该装置可以包括二维布置在基板上并从基板垂直延伸的垂直通道结构。 该装置还可以包括在垂直通道结构上的位线，并且每个位线可以共同连接到沿第一方向布置的垂直通道结构。 该装置还可以包括在与第一方向相交的第二方向上在垂直通道结构之间延伸的公共源极线和与位线设置在相同垂直电平并将公共源极线彼此电连接的源极捆扎线 。

公开(公告)号：US20160149010A1

公开(公告)日：2016-05-26

申请号：US15012979

申请日：2016-02-02

申请人： Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

发明人： Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

IPC分类号： H01L29/423 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

摘要翻译： 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。

公开(公告)号：US20140284695A1

公开(公告)日：2014-09-25

申请号：US14151288

申请日：2014-01-09

申请人： Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

发明人： Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

IPC分类号： H01L29/792

CPC分类号： H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

摘要翻译： 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。

公开(公告)号：US10181476B2

公开(公告)日：2019-01-15

申请号：US15087127

申请日：2016-03-31

申请人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

发明人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC分类号： H01L27/11582 ,  H01L27/11565

摘要： Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

公开(公告)号：US20170104000A1

公开(公告)日：2017-04-13

申请号：US15291662

申请日：2016-10-12

申请人： Joo-Hee PARK ,  Jong-Min LEE ,  Seon-Kyung KIM ,  Kee-Jeong RHO ,  Jin-hyun SHIN ,  Jong-Hyun PARK ,  Jin-Yeon WON

发明人： Joo-Hee PARK ,  Jong-Min LEE ,  Seon-Kyung KIM ,  Kee-Jeong RHO ,  Jin-hyun SHIN ,  Jong-Hyun PARK ,  Jin-Yeon WON

IPC分类号： H01L27/115 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

公开(公告)号：US09281414B2

公开(公告)日：2016-03-08

申请号：US14151288

申请日：2014-01-09

申请人： Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

发明人： Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

摘要翻译： 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。