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公开(公告)号：US20110161568A1
公开(公告)日：2011-06-30
申请号：US12876247
申请日：2010-09-07
CPC分类号： G06F13/1657 , G06F12/00 , G06F12/0246 , G06F13/1673 , G06F13/1684 , G06F13/36
摘要： The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
摘要翻译： 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。
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公开(公告)号：US07826243B2
公开(公告)日：2010-11-02
申请号：US11322442
申请日：2005-12-29
IPC分类号： G11C5/02
CPC分类号： H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
摘要： Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
摘要翻译： 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。
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公开(公告)号：US20130246694A1
公开(公告)日：2013-09-19
申请号：US13890229
申请日：2013-05-08
IPC分类号： G06F12/02
CPC分类号： G06F13/1657 , G06F12/00 , G06F12/0246 , G06F13/1673 , G06F13/1684 , G06F13/36
摘要： The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
摘要翻译： 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 一个闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。
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公开(公告)号：US08093103B2
公开(公告)日：2012-01-10
申请号：US12907023
申请日：2010-10-18
CPC分类号： H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
摘要： Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
摘要翻译： 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。
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公开(公告)号：US20110038127A1
公开(公告)日：2011-02-17
申请号：US12907023
申请日：2010-10-18
CPC分类号： H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
摘要： Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
摘要翻译： 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。
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