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1.发明授权Angular spectrum tailoring in solid immersion microscopy for circuit analysis 失效用于电路分析的固体浸液显微镜中的角度光谱裁剪公开(公告)号：US07826045B2
公开(公告)日：2010-11-02
申请号：US12020157
申请日：2008-01-25
IPC分类号： G01N21/00
CPC分类号： G01R31/311
摘要： A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译： 一种用于定位半导体芯片中的故障的方法和结构。 芯片包括电介质互连上的衬底。 包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。 衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。 芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。 如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。
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2.发明申请ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS 失效用于电路分析的固体显微镜中的角度光谱定标公开(公告)号：US20110037973A1
公开(公告)日：2011-02-17
申请号：US12911781
申请日：2010-10-26
IPC分类号： G01N21/88
CPC分类号： G01R31/311
摘要： A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译： 用于定位半导体芯片中的故障的结构。 芯片包括电介质互连上的衬底。 包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。 衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。 芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。 如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。
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公开(公告)号：US20080227247A1
公开(公告)日：2008-09-18
申请号：US12129117
申请日：2008-05-29
IPC分类号： H01L21/314
CPC分类号： H01L23/3192 , H01L21/76832 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.
摘要翻译： 本发明提供一种半导体器件，其包括在半导体衬底顶部的栅极电介质，所述半导体衬底含有邻近栅极电介质的源区和漏区; 栅极电介质顶部的栅极导体; 位于至少栅极导体侧壁上的保形介质钝化堆叠，所述保形介质钝化堆叠包括多个保形介电层，其中没有电路完全穿过堆叠; 以及与源区和漏区的接触，其中通过保形电介质钝化堆的不连续接缝基本上消除了接触和栅极导体之间的短路。 本发明还提供了形成上述半导体器件的方法。
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4.发明授权Backside unlayering of MOSFET devices for electrical and physical characterization 有权用于电气和物理表征的MOSFET器件的背面非层叠公开(公告)号：US07371689B2
公开(公告)日：2008-05-13
申请号：US11242719
申请日：2005-10-03
IPC分类号： H01L21/302
CPC分类号： H01J37/32366 , G01N1/32 , G01R31/2898 , H01J2237/3114
摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
摘要翻译： 一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。 在半导体的背面基板层内形成窗口。 产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。 这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于 后视窗，曝光。 通过CAIBE处理可以增强本发明的背面未铺层。
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5.发明授权公开(公告)号：US07112983B2
公开(公告)日：2006-09-26
申请号：US10904435
申请日：2004-11-10
申请人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
发明人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
IPC分类号： G01R31/26
CPC分类号： G01R31/2886 , G01R1/0408 , G01R31/311
摘要： An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.
摘要翻译： 用于促进半导体器件的单模背面探测的装置包括芯片保持器，其构造成用于接收附接到其上的单个集成电路管芯，所述芯片保持器相对于升降板以X-Y取向保持柔性接合。 提升环联接到提升板，提升环构造成便于在Z方向上调节提升板和芯片保持器。
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6.发明授权Backside unlayering of MOSFET devices for electrical and physical characterization 有权用于电气和物理表征的MOSFET器件的背面非层叠公开(公告)号：US07993504B2
公开(公告)日：2011-08-09
申请号：US12027563
申请日：2008-02-07
IPC分类号： C23C14/34
CPC分类号： H01J37/32366 , G01N1/32 , G01R31/2898 , H01J2237/3114
摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
摘要翻译： 一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。 在半导体的背面基板层内形成窗口。 产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。 这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于 后视窗，曝光。 通过CAIBE处理可以增强本发明的背面未铺层。
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公开(公告)号：US07397073B2
公开(公告)日：2008-07-08
申请号：US10904661
申请日：2004-11-22
IPC分类号： H01L29/76
CPC分类号： H01L23/3192 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.
摘要翻译： 本发明提供一种半导体器件，其包括在半导体衬底顶部的栅极电介质，所述半导体衬底含有邻近栅极电介质的源区和漏区; 栅极电介质顶部的栅极导体; 位于至少栅极导体侧壁上的保形介质钝化堆叠，所述保形介质钝化堆叠包括多个保形介电层，其中没有电路完全穿过堆叠; 以及与源区和漏区的接触，其中通过保形电介质钝化堆的不连续接缝基本上消除了接触和栅极导体之间的短路。 本发明还提供了形成上述半导体器件的方法。
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8.发明申请BACKSIDE UNLAYERING OF MOSFET DEVICES FOR ELECTRICAL AND PHYSICAL CHARACTERIZATION 有权用于电气和物理特性的MOSFET器件的背面分布公开(公告)号：US20080128086A1
公开(公告)日：2008-06-05
申请号：US12027563
申请日：2008-02-07
IPC分类号： H01L21/306
CPC分类号： H01J37/32366 , G01N1/32 , G01R31/2898 , H01J2237/3114
摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
摘要翻译： 一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。 在半导体的背面基板层内形成窗口。 产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。 这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于 后视窗，曝光。 通过CAIBE处理可以增强本发明的背面未铺层。
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9.发明授权Angular spectrum tailoring in solid immersion microscopy for circuit analysis 失效用于电路分析的固体浸液显微镜中的角度光谱裁剪公开(公告)号：US07961307B2
公开(公告)日：2011-06-14
申请号：US12911781
申请日：2010-10-26
IPC分类号： G01N21/00
CPC分类号： G01R31/311
摘要： A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译： 用于定位半导体芯片中的故障的结构。 芯片包括电介质互连上的衬底。 包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。 衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。 芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。 如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。
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10.发明申请ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS 失效用于电路分析的固体显微镜中的角度光谱定标公开(公告)号：US20090189630A1
公开(公告)日：2009-07-30
申请号：US12020157
申请日：2008-01-25
IPC分类号： G01R31/26
CPC分类号： G01R31/311
摘要： A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译： 一种用于定位半导体芯片中的故障的方法和结构。 芯片包括电介质互连上的衬底。 包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。 衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。 芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。 如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。
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