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1.发明授权On-chip calibrated source termination for voltage mode driver and method of calibration thereof 有权用于电压模式驱动器的片上校准源终端及其校准方法公开(公告)号：US07119611B2
公开(公告)日：2006-10-10
申请号：US10411993
申请日：2003-04-11
申请人： Eric James Wyers , Dan Stiurca , John James Paulos
发明人： Eric James Wyers , Dan Stiurca , John James Paulos
CPC分类号： H03F3/45192 , H03F2203/45726
摘要： On-chip calibrated source termination for voltage mode driver. An amplifier is disclosed having an internal amplifier with a first output and a second output, the first output interfaced to a non-inverting input through an interface. The second output is coupled to the first output through a series resistance element. The output impedance of the amplifier is determined by the ratio of the current drive of the first and second outputs. The voltage on said second output being a function of said interface and the current input to said internal amplifier.
摘要翻译： 用于电压模式驱动器的片上校准源端接。 公开了具有具有第一输出和第二输出的内部放大器的放大器，第一输出通过接口连接到非反相输入。 第二输出通过串联电阻元件耦合到第一输出端。 放大器的输出阻抗由第一和第二输出的电流驱动的比率决定。 所述第二输出端的电压是所述接口的功能，并且输入到所述内部放大器的电流。
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公开(公告)号：US07340662B1
公开(公告)日：2008-03-04
申请号：US10428326
申请日：2003-04-30
IPC分类号： G01R31/3167 , G01R31/40
CPC分类号： G01R31/3167
摘要： GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a transmit portion and a receive portion, the analog portions adaptable to interface with an analog network. The transceiver is first configured to operate in a test mode. In the test mode, the transmit portion of the digital processing section is activated to generate data to be transmitted by the transmit portion of the analog section. The receive portion of the analog section and the receive portion of the digital processing section are operated to receive data. Thereafter, the parametrics of select portions of the receive portion of the digital processing section are examined during the receipt of data by the receive portion of the analog section and processing thereof by the receive portion of the digital processing section.
摘要翻译： GBit / s收发器具有内置的自检功能。 公开了一种用于测试具有数字处理部分和模拟部分的收发器的操作的方法，每个具有发送部分和接收部分，模拟部分适于与模拟网络接口。 收发器首先配置为在测试模式下运行。 在测试模式中，数字处理部分的发送部分被激活，以产生由模拟部分的发送部分发送的数据。 操作模拟部分的接收部分和数字处理部分的接收部分以接收数据。 此后，数字处理部分的接收部分的选择部分的参数在由模拟部分的接收部分接收数据期间被数字处理部分的接收部分处理。
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公开(公告)号：US06967471B2
公开(公告)日：2005-11-22
申请号：US10754250
申请日：2004-01-09
申请人： John James Paulos
发明人： John James Paulos
摘要： Switching node regulator for sfp ethernet adaptor. A method is disclosed for regulating voltage on an integrated circuit formed on a substrate to power circuitry on the substrate. An unregulated power supply is provided as an input to the integrated circuit connected between a positive node and a reference node on the integrated circuit. Current is sourced in a first current sourcing step through drive circuitry on the substrate from the positive node to an inductor/capacitor reactive circuit external to the integrated circuit. The output of the inductor/capacitor reactive circuit comprises a filtered regulated power supply voltage that is operable to power at least a portion of the circuitry on the substrate. Current is sourced in a second current sourcing step through the drive circuitry on the substrate from the reference node to the inductor/capacitor reactive circuit when the current in the inductor is ramping down. A controller is operable to control the first and second sourcing steps to alternately source current to the inductor/capacitor reactive circuit from the positive and reference nodes. The controller is further operable to prevent substantially any current from being drawn through the substrate body during either the first current sourcing step or the second current sourcing step and delivered to the inductor/capacitor reactive circuit during ramp up or ramp down of the current in the inductor/capacitor reactive circuit and during any transition there between.
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公开(公告)号：US06665347B2
公开(公告)日：2003-12-16
申请号：US09894388
申请日：2001-06-28
IPC分类号： H03K1716
CPC分类号： H04L25/0266 , H04B3/00
摘要： Output driver for high speed Ethernet transceiver. A transmission line driver is disclosed for driving a transmission line in a first operating mode and in a second operating mode. The first and second operating modes operate substantially exclusive of each other. A current driver is provided for driving the transmission line in the first operating mode from a first data generator and at a first output voltage. A voltage driver is provided for driving the transmission line in the second operating mode from a second data generator at a second output voltage through a load, such that the current driver and the voltage driver operate independent of each other.
摘要翻译： 高速以太网收发器的输出驱动器。 公开了用于在第一操作模式和第二操作模式下驱动传输线的传输线驱动器。 第一和第二操作模式基本上彼此排斥。 提供电流驱动器，用于在第一操作模式下从第一数据发生器和第一输出电压驱动传输线。 提供电压驱动器，用于通过负载以第二输出电压从第二数据发生器以第二操作模式驱动传输线，使得电流驱动器和电压驱动器彼此独立地操作。
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5.发明授权
公开(公告)号：US6011501A
公开(公告)日：2000-01-04
申请号：US224389
申请日：1998-12-31
申请人： Xue-Mei Gong , John James Paulos , Mark Alexander , Eric Gaalaas , Dylan Hester
发明人： Xue-Mei Gong , John James Paulos , Mark Alexander , Eric Gaalaas , Dylan Hester
摘要： Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.
摘要翻译： 示出了数模转换电路100，其包括用于以1位格式处理数据的路径。 模拟有限脉冲响应滤波器300的第一部分包括用于接收1比特格式的数据流的预选数量的延迟元件301，并且响应地输出多个信号。 开关电容器数模转换器106形成有限脉冲响应滤波器301的第二部分，并且具有多个元件，每个元件接收所选择的多个信号中的一个以实现一组滤波器系数，转换器106将多个 的信号并输出模拟数据流。
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公开(公告)号：US07132849B2
公开(公告)日：2006-11-07
申请号：US10852586
申请日：2004-05-24
IPC分类号： G06F7/38 , G06F17/50 , H03K19/173 , H03K19/00
CPC分类号： H03K19/1731
摘要： Method and apparatus for configuring the operation of an integrated circuit. An integrated circuit with external programming capabilities is disclosed. A pin current source is provided for interfacing with at least one pin on the integrated circuit to control current flow there through to an external load interfaced to the at least one pin external to the integrated circuit. The external load has at least two discrete values. A voltage detector detects the voltage on the at least one pin and a state detector then compares the voltage on the at least one pin to at least two discrete voltage thresholds. Each of the discrete voltages is associated with a separate value of a control word, and the state detector is operable to determine the value of the control word associated with the detected voltage. The state detector then outputs the determined value of the control word.
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公开(公告)号：US06262616B1
公开(公告)日：2001-07-17
申请号：US09415136
申请日：1999-10-08
IPC分类号： G11C514
CPC分类号： H03F1/301 , H03F2200/331 , H03K5/133 , H03K2005/0013 , H03K2005/00202 , H03M3/458 , H03M3/50
摘要： A technique for compensating for supply voltage variations in a delay circuit by utilizing a bias circuit to maintain the delay substantially constant with respect to the supply voltage. The bias circuit generates a bias current having a fixed component and a variable component, in which the variable component varies proportionately to variations in the supply voltage to maintain the delay substantially constant.
摘要翻译： 一种用于通过利用偏置电路来补偿延迟电路中的电源电压变化以维持相对于电源电压基本恒定的延迟的技术。 偏置电路产生具有固定分量和可变分量的偏置电流，其中可变分量与电源电压的变化成比例地变化，以保持延迟基本恒定。
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